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    SEMICONDUCTOR DEVICE AND ELECTRONIC SYSTEM INCLUDING THE SAME
    2.
    发明申请
    SEMICONDUCTOR DEVICE AND ELECTRONIC SYSTEM INCLUDING THE SAME 有权

    公开(公告)号：US20220352194A1

    公开(公告)日：2022-11-03

    申请号：US17557501

    申请日：2021-12-21

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Youngmo Ku ,  Wookhyoung Lee ,  Kang-Sup Roh ,  Seongjun Seo ,  Yongin Cho

    IPC: H01L27/11556 ,  H01L27/11582 ,  H01L27/11524 ,  H01L27/1157 ,  H01L23/522

    Abstract: Disclosed is a semiconductor device comprising a substrate including a cell array region and a connection region, an electrode structure extending in a first direction on the substrate and including vertically stacked electrodes having pad sections arranged stepwise on the connection region, a first contact plug connected to a first one of the pad sections, a pair of first vertical structures that penetrate the first one of the pad sections and are spaced apart from each other in a first direction by a first distance, a second contact plug connected to a second one of the pad section and having a vertical length that is greater than that of the first contact plug, and a pair of second vertical structures that penetrate the second one of the pad sections and are spaced apart from each other in the first direction by a second distance that is greater than the first distance.

    Semiconductor devices and data storage systems including the same
    4.
    发明授权
    Semiconductor devices and data storage systems including the same 有权

    公开(公告)号：US12120876B2

    公开(公告)日：2024-10-15

    申请号：US17679268

    申请日：2022-02-24

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Seokcheon Baek ,  Miram Kwon ,  Seongjun Seo ,  Younghwan Son

    IPC: H10B43/27 ,  H01L27/06 ,  H10B43/40

    CPC classification number: H10B43/27 ,  H01L27/0688 ,  H10B43/40

    Abstract: A semiconductor device includes a first substrate, circuit elements, lower interconnection lines, a second substrate, gate electrodes stacked on the second substrate to be spaced apart from each other in a first direction and forming first and second stack structures, channel structures penetrating through the gate electrodes, and first and second contact plugs penetrating through the first and second stack structures, respectively, and connected to the gate electrodes. The first stack structure has first pad areas in which the gate electrodes extend further than upper gate electrodes, respectively, and are connected to the first contact plugs, respectively. The second stack structure has second pad areas in which the gate electrodes extend further than upper gate electrodes, respectively, and are connected to the second contact plugs, respectively. The first and second pad areas are offset in relation to each other so as not to overlap each other in the first direction.

    Three-dimensional semiconductor memory devices
    7.
    发明授权
    Three-dimensional semiconductor memory devices 有权

    公开(公告)号：US10937797B2

    公开(公告)日：2021-03-02

    申请号：US16243236

    申请日：2019-01-09

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Seongjun Seo ,  Hyun-Seok Na ,  Heejueng Lee ,  Heung Jin Joo

    IPC: H01L27/11575 ,  H01L27/11524 ,  H01L27/11556 ,  H01L27/11548 ,  H01L29/06 ,  H01L27/1157 ,  H01L27/11582 ,  H01L27/11573 ,  H01L27/11529 ,  H01L27/11565

    Abstract: A three-dimensional semiconductor memory device may include a substrate including a cell array region, a peripheral circuit region, and a connection region between the cell array region and the peripheral circuit region. The memory device may include an electrode structure extending from the cell array region toward the connection region and comprising electrodes stacked on the substrate, a horizontal gate dielectric layer between the electrode structure and the substrate and including a first portion on the cell array region and a second portion on the connection region, the second portion thicker than the first portion in the vertical direction, first vertical channels on the cell array region and penetrating the electrode structure and the first portion of the horizontal gate dielectric layer, and second vertical channels on the connection region and penetrating the electrode structure and the second portion of the horizontal gate dielectric layer.

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