公开(公告)号：US20200083296A1

公开(公告)日：2020-03-12

申请号：US16685394

申请日：2019-11-15

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Joyoung PARK ,  Seok-Won LEE ,  Seongjun SEO

IPC: H01L27/24 ,  H01L27/11556 ,  H01L27/11582 ,  H01L27/11519 ,  H01L27/11548 ,  H01L27/11565 ,  H01L27/11575 ,  H01L27/06

Abstract: A three-dimensional semiconductor device is provided as follows. A substrate includes a contact region, a dummy region, and a cell array region. A stack structure includes electrodes vertically stacked on the substrate. The electrodes are stacked to have a first stepwise structure on the contact region and a second stepwise structure in the dummy region. Ends of at least two adjacent electrodes in the second stepwise structure have first sidewalls vertically aligned so that horizontal positions of the first sidewalls are substantially the same.

公开(公告)号：US20250017013A1

公开(公告)日：2025-01-09

申请号：US18887445

申请日：2024-09-17

Applicant: Samsung Electronics Co., Ltd.

Inventor： Seokcheon BAEK ,  Miram KWON ,  Seongjun SEO ,  Younghwan SON

IPC: H10B43/27 ,  H01L27/06 ,  H10B43/40

Abstract: A semiconductor device includes a first substrate, circuit elements, lower interconnection lines, a second substrate, gate electrodes stacked on the second substrate to be spaced apart from each other in a first direction and forming first and second stack structures, channel structures penetrating through the gate electrodes, and first and second contact plugs penetrating through the first and second stack structures, respectively, and connected to the gate electrodes. The first stack structure has first pad areas in which the gate electrodes extend further than upper gate electrodes, respectively, and are connected to the first contact plugs, respectively. The second stack structure has second pad areas in which the gate electrodes extend further than upper gate electrodes, respectively, and are connected to the second contact plugs, respectively. The first and second pad areas are offset in relation to each other so as not to overlap each other in the first direction.

公开(公告)号：US20190304991A1

公开(公告)日：2019-10-03

申请号：US16243236

申请日：2019-01-09

Applicant: Samsung Electronics Co., Ltd.

Inventor： Seongjun SEO ,  Hyun-Seok NA ,  Heejueng Lee ,  Heung Jin Joo

IPC: H01L27/11575 ,  H01L27/11524 ,  H01L27/11556 ,  H01L27/11548 ,  H01L27/11529 ,  H01L27/1157 ,  H01L27/11582 ,  H01L27/11573 ,  H01L29/06

Abstract: A three-dimensional semiconductor memory device may include a substrate including a cell array region, a peripheral circuit region, and a connection region between the cell array region and the peripheral circuit region. The memory device may include an electrode structure extending from the cell array region toward the connection region and comprising electrodes stacked on the substrate, a horizontal gate dielectric layer between the electrode structure and the substrate and including a first portion on the cell array region and a second portion on the connection region, the second portion thicker than the first portion in the vertical direction, first vertical channels on the cell array region and penetrating the electrode structure and the first portion of the horizontal gate dielectric layer, and second vertical channels on the connection region and penetrating the electrode structure and the second portion of the horizontal gate dielectric layer.

公开(公告)号：US20230422509A1

公开(公告)日：2023-12-28

申请号：US18336497

申请日：2023-06-16

Applicant: Samsung Electronics Co., Ltd.

Inventor： Seokcheon BAEK ,  Seongjun SEO

IPC: H10B43/35 ,  H10B41/35 ,  H10B41/27 ,  H10B43/27

CPC classification number: H10B43/35 ,  H10B41/35 ,  H10B41/27 ,  H10B43/27

Abstract: A semiconductor device is provided. The semiconductor device includes a substrate including a memory cell region and a connection region, a plurality of gate electrodes in the memory cell region and arranged apart from one another in a vertical direction, the gate electrodes including a ground selection line and a plurality of word lines, a pair of gate stack separation insulation layers passing through the gate electrodes and extending in a first horizontal direction in the memory cell region and the connection region, and a pad structure including a plurality of pad layers in the connection region, connected to respective ones of the gate electrodes, arranged in a staircase shape in the first horizontal direction and in a second horizontal direction, the ground selection line including a plurality of ground selection line cut regions each being apart from edges of the pad layers in the second horizontal direction.

公开(公告)号：US20230084557A1

公开(公告)日：2023-03-16

申请号：US17869909

申请日：2022-07-21

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Seokcheon BAEK ,  Miram KWON ,  Seongjun SEO

IPC: H01L27/11582 ,  H01L27/11556 ,  H01L27/11524 ,  H01L27/11526 ,  H01L27/11573 ,  H01L27/1157 ,  H01L27/11519 ,  H01L27/11565

Abstract: A semiconductor device includes a substrate having cell and connection regions, and a stack structure having dielectric layers and electrodes that are vertically and alternately stacked on the substrate. The stack structure includes a first pad part, a first fence part, a second pad part, and a second fence part that are sequentially arranged along a first direction. Each of the first and second pad parts has a first stepwise structure formed along the first direction and a second stepwise structure formed along a second direction that intersects the first direction, and each of the first and second fence parts includes dummy electrodes at the same levels as the electrodes and spaced apart from the electrodes. Sidewalls of the electrodes that define second stepwise structure of the second part are offset from sidewalls of the dummy electrodes that define second dummy stepwise structure of the first pad part.

公开(公告)号：US20220392916A1

公开(公告)日：2022-12-08

申请号：US17679268

申请日：2022-02-24

Applicant: Samsung Electronics Co., Ltd.

Inventor： Seokcheon BAEK ,  Miram KWON ,  Seongjun SEO ,  Younghwan SON

IPC: H01L27/11582 ,  H01L27/11573 ,  H01L27/06

Abstract: A semiconductor device includes a first substrate, circuit elements, lower interconnection lines, a second substrate, gate electrodes stacked on the second substrate to be spaced apart from each other in a first direction and forming first and second stack structures, channel structures penetrating through the gate electrodes, and first and second contact plugs penetrating through the first and second stack structures, respectively, and connected to the gate electrodes. The first stack structure has first pad areas in which the gate electrodes extend further than upper gate electrodes, respectively, and are connected to the first contact plugs, respectively. The second stack structure has second pad areas in which the gate electrodes extend further than upper gate electrodes, respectively, and are connected to the second contact plugs, respectively. The first and second pad areas are offset in relation to each other so as not to overlap each other in the first direction.