公开(公告)号：US10529736B2

公开(公告)日：2020-01-07

申请号：US16138416

申请日：2018-09-21

Applicant: Samsung Electronics Co., Ltd.

Inventor： Min Sung Song ,  Heung Jin Joo ,  Kwan Yong Kim ,  Jin Woo Park ,  Du Heon Song ,  He Jueng Lee ,  Myung Ho Jung

IPC: H01L27/11582 ,  H01L27/1157 ,  H01L27/11573 ,  G11C16/08

Abstract: In some embodiments, 3-dimensional semiconductor memory device includes a semiconductor substrate extending horizontally in a first direction and a second direction crossing the first direction. A stacked memory cell array is formed on the semiconductor substrate. The memory device further includes a separation pattern including a plurality of separation lines extending in the first direction and arranged in the second direction, and dividing the stacked memory cell array into a plurality of memory cell structures extending in the first direction and arranged in the second direction. An upper insulating layer is formed above the plurality of memory cell structures and separation lines, and a passivation layer is formed above the upper insulating layer. The passivation layer includes a plurality of first regions having a first vertical thickness. A plurality of gap regions in the passivation layer are formed between the plurality of first regions. The plurality of first regions vertically overlap the plurality of memory cell structures, and the plurality of gap regions vertically overlap the plurality of separation lines.

公开(公告)号：US10896917B2

公开(公告)日：2021-01-19

申请号：US16722155

申请日：2019-12-20

Applicant: Samsung Electronics Co., Ltd.

Inventor： Min Sung Song ,  Heung Jin Joo ,  Kwan Yong Kim ,  Jin Woo Park ,  Du Heon Song ,  He Jueng Lee ,  Myung Ho Jung

IPC: H01L27/1157 ,  H01L27/11582 ,  H01L27/11573 ,  H01L27/11565 ,  H01L27/11575 ,  G11C16/08

Abstract: In some embodiments, 3-dimensional semiconductor memory device includes a semiconductor substrate extending horizontally in a first direction and a second direction crossing the first direction. A stacked memory cell array is formed on the semiconductor substrate. The memory device further includes a separation pattern including a plurality of separation lines extending in the first direction and arranged in the second direction, and dividing the stacked memory cell array into a plurality of memory cell structures extending in the first direction and arranged in the second direction. An upper insulating layer is formed above the plurality of memory cell structures and separation lines, and a passivation layer is formed above the upper insulating layer. The passivation layer includes a plurality of first regions having a first vertical thickness. A plurality of gap regions in the passivation layer are formed between the plurality of first regions. The plurality of first regions vertically overlap the plurality of memory cell structures, and the plurality of gap regions vertically overlap the plurality of separation lines.

公开(公告)号：US20190304991A1

公开(公告)日：2019-10-03

申请号：US16243236

申请日：2019-01-09

Applicant: Samsung Electronics Co., Ltd.

Inventor： Seongjun SEO ,  Hyun-Seok NA ,  Heejueng Lee ,  Heung Jin Joo

IPC: H01L27/11575 ,  H01L27/11524 ,  H01L27/11556 ,  H01L27/11548 ,  H01L27/11529 ,  H01L27/1157 ,  H01L27/11582 ,  H01L27/11573 ,  H01L29/06

Abstract: A three-dimensional semiconductor memory device may include a substrate including a cell array region, a peripheral circuit region, and a connection region between the cell array region and the peripheral circuit region. The memory device may include an electrode structure extending from the cell array region toward the connection region and comprising electrodes stacked on the substrate, a horizontal gate dielectric layer between the electrode structure and the substrate and including a first portion on the cell array region and a second portion on the connection region, the second portion thicker than the first portion in the vertical direction, first vertical channels on the cell array region and penetrating the electrode structure and the first portion of the horizontal gate dielectric layer, and second vertical channels on the connection region and penetrating the electrode structure and the second portion of the horizontal gate dielectric layer.

公开(公告)号：US10937797B2

公开(公告)日：2021-03-02

申请号：US16243236

申请日：2019-01-09

Applicant: Samsung Electronics Co., Ltd.

Inventor： Seongjun Seo ,  Hyun-Seok Na ,  Heejueng Lee ,  Heung Jin Joo

IPC: H01L27/11575 ,  H01L27/11524 ,  H01L27/11556 ,  H01L27/11548 ,  H01L29/06 ,  H01L27/1157 ,  H01L27/11582 ,  H01L27/11573 ,  H01L27/11529 ,  H01L27/11565

Abstract: A three-dimensional semiconductor memory device may include a substrate including a cell array region, a peripheral circuit region, and a connection region between the cell array region and the peripheral circuit region. The memory device may include an electrode structure extending from the cell array region toward the connection region and comprising electrodes stacked on the substrate, a horizontal gate dielectric layer between the electrode structure and the substrate and including a first portion on the cell array region and a second portion on the connection region, the second portion thicker than the first portion in the vertical direction, first vertical channels on the cell array region and penetrating the electrode structure and the first portion of the horizontal gate dielectric layer, and second vertical channels on the connection region and penetrating the electrode structure and the second portion of the horizontal gate dielectric layer.