公开(公告)号：US20220148634A1

公开(公告)日：2022-05-12

申请号：US17375318

申请日：2021-07-14

Applicant: Samsung Electronics Co., Ltd.

Inventor： Hyeok Jun CHOI ,  Young Chul CHO ,  Seung Jin PARK ,  Jae Woo PARK ,  Young Don CHOI ,  Jung Hwan CHOI

IPC: G11C7/22 ,  G11C7/10 ,  H03L7/081

Abstract: A memory device in which reliability of a clock signal is improved is provided. The memory device comprises a data module including a clock signal generator configured to receive an internal clock signal from a buffer, and to generate a first internal clock signal, a second internal clock signal, a third internal clock signal, and a fourth internal clock signal having different phases, on the basis of the internal clock signal, and a first data signal generator configured to generate a first data signal on the basis of first data and the first internal clock signal, generate a second data signal on the basis of second data and the second internal clock signal, generate a third data signal on the basis of third data and the third internal clock signal, and generate a fourth data signal on the basis of fourth data and the fourth internal clock signal.

公开(公告)号：US20230298645A1

公开(公告)日：2023-09-21

申请号：US18323550

申请日：2023-05-25

Applicant: Samsung Electronics Co., Ltd.

Inventor： Hyeok Jun CHOI ,  Young Chul CHO ,  Seung Jin PARK ,  Jae Woo PARK ,  Young Don CHOI ,  Jung Hwan CHOI

IPC: G11C7/22 ,  H03L7/081 ,  G11C7/10

CPC classification number: G11C7/222 ,  G11C7/1057 ,  G11C7/1084 ,  H03L7/0814

Abstract: A memory device in which reliability of a clock signal is improved is provided. The memory device comprises a data module including a clock signal generator configured to receive an internal clock signal from a buffer, and to generate a first internal clock signal, a second internal clock signal, a third internal clock signal, and a fourth internal clock signal having different phases, on the basis of the internal clock signal, and a first data signal generator configured to generate a first data signal on the basis of first data and the first internal clock signal, generate a second data signal on the basis of second data and the second internal clock signal, generate a third data signal on the basis of third data and the third internal clock signal, and generate a fourth data signal on the basis of fourth data and the fourth internal clock signal.