公开(公告)号：US20220138045A1

公开(公告)日：2022-05-05

申请号：US17398158

申请日：2021-08-10

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Jun Young PARK ,  Young-Hoon SON ,  Hyun-Yoon CHO ,  Young Don CHOI ,  Jung Hwan CHOI

IPC: G06F11/10 ,  H03M13/29 ,  G06F1/08

Abstract: A memory device includes a multiphase clock generator which generates a plurality of divided clock signals, a first error correction block which receives a first divided clock signal among the plurality of divided clock signals, a first data multiplexer which transmits first least significant bit data corresponding to the first divided clock signal, a second error correction block which receives the first divided clock signal, and a second data multiplexer which transmits first most significant bit data corresponding to the first divided clock signal. The first error correction block receives the first least significant bit data and corrects a toggle timing of the first least significant bit data. The second error correction block receives the first most significant bit data and corrects a toggle time of the first most significant bit data.

公开(公告)号：US20230138845A1

公开(公告)日：2023-05-04

申请号：US17810929

申请日：2022-07-06

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Joo Hwan KIM ,  Su Cheol LEE ,  Jin Do BYUN ,  Eun Seok SHIN ,  Young Don CHOI ,  Jung Hwan CHOI

IPC: G06F3/06 ,  G11C11/4096

Abstract: A memory device, a host device and a method of operating the memory device are provided. The memory device includes a data signal generator configured to provide a data signal to a transmission driver, the transmission driver configured to output a multi-level signal having any one of first to third signal levels based on the data signal, a command decoder configured to receive a feedback signal from outside of the memory device and decode the feedback signal, a data signal controller configured to adjust the data signal based on a decoding result of the command decoder, and a drive strength controller configured to adjust at least one of the first to third signal levels based on the decoding result of the command decoder.

公开(公告)号：US20220148634A1

公开(公告)日：2022-05-12

申请号：US17375318

申请日：2021-07-14

Applicant: Samsung Electronics Co., Ltd.

Inventor： Hyeok Jun CHOI ,  Young Chul CHO ,  Seung Jin PARK ,  Jae Woo PARK ,  Young Don CHOI ,  Jung Hwan CHOI

IPC: G11C7/22 ,  G11C7/10 ,  H03L7/081

Abstract: A memory device in which reliability of a clock signal is improved is provided. The memory device comprises a data module including a clock signal generator configured to receive an internal clock signal from a buffer, and to generate a first internal clock signal, a second internal clock signal, a third internal clock signal, and a fourth internal clock signal having different phases, on the basis of the internal clock signal, and a first data signal generator configured to generate a first data signal on the basis of first data and the first internal clock signal, generate a second data signal on the basis of second data and the second internal clock signal, generate a third data signal on the basis of third data and the third internal clock signal, and generate a fourth data signal on the basis of fourth data and the fourth internal clock signal.

公开(公告)号：US20230298645A1

公开(公告)日：2023-09-21

申请号：US18323550

申请日：2023-05-25

Applicant: Samsung Electronics Co., Ltd.

Inventor： Hyeok Jun CHOI ,  Young Chul CHO ,  Seung Jin PARK ,  Jae Woo PARK ,  Young Don CHOI ,  Jung Hwan CHOI

IPC: G11C7/22 ,  H03L7/081 ,  G11C7/10

CPC classification number: G11C7/222 ,  G11C7/1057 ,  G11C7/1084 ,  H03L7/0814

Abstract: A memory device in which reliability of a clock signal is improved is provided. The memory device comprises a data module including a clock signal generator configured to receive an internal clock signal from a buffer, and to generate a first internal clock signal, a second internal clock signal, a third internal clock signal, and a fourth internal clock signal having different phases, on the basis of the internal clock signal, and a first data signal generator configured to generate a first data signal on the basis of first data and the first internal clock signal, generate a second data signal on the basis of second data and the second internal clock signal, generate a third data signal on the basis of third data and the third internal clock signal, and generate a fourth data signal on the basis of fourth data and the fourth internal clock signal.

公开(公告)号：US20230143365A1

公开(公告)日：2023-05-11

申请号：US17852664

申请日：2022-06-29

Applicant: Samsung Electronics Co., Ltd.

Inventor： Joo Hwan KIM ,  Jun Young PARK ,  Jin Do BYUN ,  Kwang Seob SHIN ,  Eun Seok SHIN ,  Hyun-Yoon CHO ,  Young Don CHOI ,  Jung Hwan CHOI

IPC: G11C7/10

CPC classification number: G11C7/1048 ,  G11C2207/2254

Abstract: A method includes measuring a linearity of a first pull-up circuit, a second pull-up circuit, a third pull-up circuit, a first pull-down circuit, a second pull-down circuit and a third pull-down circuit using an initial pull-up code and an initial pull-down code, each of the first pull-up circuit, the second pull-up circuit and the third pull-up circuit having a respective resistance value determined based on a respective pull-up code, and each of the first pull-down circuit, the second pull-down circuit and the third pull-down circuit having a respective resistance value determined based on a respective pull-down code, and determining a calibration setting indicator based on the measurement result, the calibration setting indicator indicating a calibration method of a transmission driver including the first pull-up circuit, the second pull-up circuit, the third pull-up circuit, the first pull-down circuit, the second pull-down circuit and the third pull-down circuit.

公开(公告)号：US20200014383A1

公开(公告)日：2020-01-09

申请号：US16206070

申请日：2018-11-30

Applicant: Samsung Electronics Co., Ltd.

Inventor： Dae Hoon NA ,  Seon Kyoo LEE ,  Jeong Don IHM ,  Byung Hoon JEONG ,  Young Don CHOI

IPC: H03K17/22 ,  H01L25/065 ,  H01L23/48

Abstract: A semiconductor package including a first master-slave status circuit configured to store one of a first signal or a second signal independently from a second master-slave status circuit, store the first signal in response to receiving a first initial signal from a first initialization circuit, the second master-slave status circuit configured to store one of the first signal or the second signal, store the first signal in response to receiving a second initial signal from a second initialization circuit, the first initialization circuit configured to provide the first initial signal to the first master-slave status circuit, the second initialization circuit configured to provide the second initial signal to the second master-slave status circuit, and a first master-slave determination circuit connected to the second master-slave status circuit, the first master-slave determination circuit configured to provide the second signal to the second master-slave status circuit may be provided.