公开(公告)号：US20230298645A1

公开(公告)日：2023-09-21

申请号：US18323550

申请日：2023-05-25

Applicant: Samsung Electronics Co., Ltd.

Inventor： Hyeok Jun CHOI ,  Young Chul CHO ,  Seung Jin PARK ,  Jae Woo PARK ,  Young Don CHOI ,  Jung Hwan CHOI

IPC: G11C7/22 ,  H03L7/081 ,  G11C7/10

CPC classification number: G11C7/222 ,  G11C7/1057 ,  G11C7/1084 ,  H03L7/0814

Abstract: A memory device in which reliability of a clock signal is improved is provided. The memory device comprises a data module including a clock signal generator configured to receive an internal clock signal from a buffer, and to generate a first internal clock signal, a second internal clock signal, a third internal clock signal, and a fourth internal clock signal having different phases, on the basis of the internal clock signal, and a first data signal generator configured to generate a first data signal on the basis of first data and the first internal clock signal, generate a second data signal on the basis of second data and the second internal clock signal, generate a third data signal on the basis of third data and the third internal clock signal, and generate a fourth data signal on the basis of fourth data and the fourth internal clock signal.

公开(公告)号：US20220148634A1

公开(公告)日：2022-05-12

申请号：US17375318

申请日：2021-07-14

Applicant: Samsung Electronics Co., Ltd.

Inventor： Hyeok Jun CHOI ,  Young Chul CHO ,  Seung Jin PARK ,  Jae Woo PARK ,  Young Don CHOI ,  Jung Hwan CHOI

IPC: G11C7/22 ,  G11C7/10 ,  H03L7/081

Abstract: A memory device in which reliability of a clock signal is improved is provided. The memory device comprises a data module including a clock signal generator configured to receive an internal clock signal from a buffer, and to generate a first internal clock signal, a second internal clock signal, a third internal clock signal, and a fourth internal clock signal having different phases, on the basis of the internal clock signal, and a first data signal generator configured to generate a first data signal on the basis of first data and the first internal clock signal, generate a second data signal on the basis of second data and the second internal clock signal, generate a third data signal on the basis of third data and the third internal clock signal, and generate a fourth data signal on the basis of fourth data and the fourth internal clock signal.

公开(公告)号：US20240080228A1

公开(公告)日：2024-03-07

申请号：US18134141

申请日：2023-04-13

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Jin Ook JUNG ,  Jae Woo PARK ,  Myoung Bo KWAK ,  Young Min KU ,  Kyoung Jun ROH ,  Jung Hwan CHOI

IPC: H04L25/03

CPC classification number: H04L25/03006

Abstract: A data receiving device may include a dummy stage block. The dummy stage block may include m dummy stages, wherein m is a natural number greater than or equal to two. Each of the m dummy stages may be configured to remove inter-symbol interference (ISI) from a dummy input signal using dummy coefficient information to generate a dummy output signal free of the ISI. Each of the m dummy stages may be further configured to output the dummy output signal. A normal stage block may include n normal stages, wherein n is a natural number greater than or equal to two. Each of the n normal stages may be configured to remove ISI from an input signal using coefficient information to generate an output signal free of the ISI and may be further configured to output the output signal.

公开(公告)号：US20230057178A1

公开(公告)日：2023-02-23

申请号：US17744067

申请日：2022-05-13

Applicant: Samsung Electronics Co., Ltd.

Inventor： Kyoung Jun ROH ,  Jae Woo PARK ,  Jun Han CHOI ,  Myoung Bo KWAK ,  Jung Hwan CHOI

IPC: G05F1/56 ,  G11C5/14 ,  G11C7/10 ,  H03F3/45

Abstract: A semiconductor device including an error amplifier configured to receive a voltage of an output node and a reference voltage, a flipped voltage follower (FVF) circuit configured to receive an output of the error amplifier and maintain the voltage of the output node at the reference voltage, and a bias current control circuit configured to receive first to third mode signals, control a magnitude of a bias current flowing through the FVF circuit based on the first to third mode signals, control the bias current of a first magnitude, based on the first mode signal, control the bias current of a second magnitude smaller than the first magnitude, based on the second mode signal, and control the bias current of a third magnitude smaller than the second magnitude, based on the third mode signal.