公开(公告)号：US20210193683A1

公开(公告)日：2021-06-24

申请号：US17029475

申请日：2020-09-23

Applicant: Samsung Electronics Co., Ltd.

Inventor： Gi Young YANG ,  Hyeon Gyu YOU ,  Ga Room KIM ,  Jin Young LIM ,  In Gyum KIM ,  Hak Chul JUNG

IPC: H01L27/118 ,  G06F30/392 ,  G11C11/412 ,  G11C5/06 ,  H01L23/528 ,  H01L27/02

Abstract: An integrated circuit including a first active region and a second active region extending in a first direction and spaced apart from each other in a second direction intersecting the first direction; a power rail and a ground rail extending in the first direction and spaced apart from the first and second active regions and each other in the second direction; source/drain contacts extending in the second direction on at least a portion of the first or second active region, gate structures extending in the second direction and on at least a portion of the first and second active regions, a power rail configured to supply power through source/drain contact vias, and a ground rail configured to supply a ground voltage through source/drain contact vias.

公开(公告)号：US20240243134A1

公开(公告)日：2024-07-18

申请号：US18617569

申请日：2024-03-26

Applicant: Samsung Electronics Co., Ltd.

Inventor： Hyeon Gyu YOU ,  In Gyum KIM ,  Gi Young YANG ,  Ji Su YU ,  Jin Young LIM ,  Hak Chul JUNG

IPC: H01L27/118 ,  H01L27/02

CPC classification number: H01L27/11807 ,  H01L27/0207 ,  H01L2027/11812 ,  H01L2027/1182 ,  H01L2027/11866 ,  H01L2027/11875 ,  H01L2027/11881 ,  H01L2027/11887

Abstract: An integrated circuit includes a first standard cell including a first first-type transistor, a first second-type transistor, a third second-type transistor, and a third first-type transistor, a second standard cell including a second first-type transistor, a second second-type transistor, a fourth second-type transistor and a fourth first-type transistor, a plurality of wiring layers which are disposed on the first and second standard cells and includes a first wiring layer, a second wiring layer, and a third wiring layer sequentially stacked. A source contact of the first first-type transistor and a source contact of the second first-type transistor are electrically connected through a first power rail of the plurality of wiring layers, and a source contact of the third first-type transistor and a source contact of the fourth first-type transistor are electrically connected through a second power rail of the plurality of wiring layers.

公开(公告)号：US20220115406A1

公开(公告)日：2022-04-14

申请号：US17561887

申请日：2021-12-24

Applicant: Samsung Electronics Co., Ltd.

Inventor： Hyeon Gyu YOU ,  In Gyum KIM ,  Gi Young YANG ,  Ji Su YU ,  Jin Young LIM ,  Hak Chul JUNG

IPC: H01L27/118 ,  H01L27/02

Abstract: An integrated circuit includes a first standard cell including a first first-type transistor, a first second-type transistor, a third second-type transistor, and a third first-type transistor, a second standard cell including a second first-type transistor, a second second-type transistor, a fourth second-type transistor and a fourth first-type transistor, a plurality of wiring layers which are disposed on the first and second standard cells and includes a first wiring layer, a second wiring layer, and a third wiring layer sequentially stacked. A source contact of the first first-type transistor and a source contact of the second first-type transistor are electrically connected through a first power rail of the plurality of wiring layers, and a source contact of the third first-type transistor and a source contact of the fourth first-type transistor are electrically connected through a second power rail of the plurality of wiring layers.

公开(公告)号：US20210134837A1

公开(公告)日：2021-05-06

申请号：US16888677

申请日：2020-05-30

Applicant: Samsung Electronics Co., Ltd.

Inventor： Hyeon Gyu YOU ,  In Gyum KIM ,  Gi Young YANG ,  Ji Su YU ,  Jin Young LIM ,  Hak Chul JUNG

IPC: H01L27/118 ,  H01L27/02

Abstract: An integrated circuit includes a first standard cell including a first first-type transistor, a first second-type transistor, a third second-type transistor, and a third first-type transistor, a second standard cell including a second first-type transistor, a second second-type transistor, a fourth second-type transistor and a fourth first-type transistor, a plurality of wiring layers which are disposed on the first and second standard cells and includes a first wiring layer, a second wiring layer, and a third wiring layer sequentially stacked. A source contact of the first first-type transistor and a source contact of the second first-type transistor are electrically connected through a first power rail of the plurality of wiring layers, and a source contact of the third first-type transistor and a source contact of the fourth first-type transistor are electrically connected through a second power rail of the plurality of wiring layers.