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    INTEGRATED CIRCUIT INCLUDING STANDARD CELLS
    3.
    发明申请
    INTEGRATED CIRCUIT INCLUDING STANDARD CELLS 有权

    公开(公告)号：US20210313310A1

    公开(公告)日：2021-10-07

    申请号：US17158109

    申请日：2021-01-26

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Ji Su YU ,  Jae-Woo SEO ,  Sanghoon BAEK ,  Hyeon Gyu YOU

    IPC: H01L27/02 ,  H01L23/528 ,  H01L27/092 ,  H01L29/06 ,  H01L29/423 ,  H01L29/786 ,  G06F30/392

    Abstract: An integrated circuit including a plurality of standard cells is provided. The integrated circuit includes a first standard cell group including at least two first standard cells, a second standard cell group adjacent to the first standard cell group in a first direction, the second standard cell group including at least one second standard cell, and a first insulating gate bordered by one side of at least one of the first standard cells and one side of the at least one second standard cell, wherein each of the first and second standard cells includes a p-type transistor (pFET) and an n-type transistor (nFET) which are integrated, wherein each of the first and second standard cells has first wiring lines of different designs, and wherein each of the first and second standard cells has the same or different placement of an active region according to the corresponding design.

    INTEGRATED CIRCUITS INCLUDING INTEGRATED STANDARD CELL STRUCTURE
    4.
    发明申请
    INTEGRATED CIRCUITS INCLUDING INTEGRATED STANDARD CELL STRUCTURE 有权

    公开(公告)号：US20210167090A1

    公开(公告)日：2021-06-03

    申请号：US17027211

    申请日：2020-09-21

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Ji Su YU ,  Jae-Ho PARK ,  Sanghoon BAEK ,  Hyeon Gyu YOU ,  Seung Young LEE ,  Seung Man LIM

    IPC: H01L27/118 ,  H01L27/02

    Abstract: An integrated circuit includes a first standard cell including a first p-type transistor, a first n-type transistor, a first gate stack intersecting first and second active regions, first extended source/drain contacts on a first side of the first gate stack, a first normal source/drain contact on a second side of the first gate stack, a first gate via connected to the first gate stack, and a first source/drain via connected to the first normal source/drain contact, a second standard cell adjacent the first standard cell and including a second p-type transistor, a second n-type transistor, a second gate stack intersecting the first and second active regions, and a second gate via connected to the second gate stack, an input wiring connected to the first gate via, and an output wiring at a same level as the input wiring to connect the first source/drain via and the second gate via.

    SEMICONDUCTOR DEVICE, LAYOUT DESIGN METHOD FOR THE SAME AND METHOD FOR FABRICATING THE SAME
    5.
    发明申请
    SEMICONDUCTOR DEVICE, LAYOUT DESIGN METHOD FOR THE SAME AND METHOD FOR FABRICATING THE SAME 有权

    公开(公告)号：US20210104611A1

    公开(公告)日：2021-04-08

    申请号：US16857288

    申请日：2020-04-24

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Ji Su YU ,  Hyeon Gyu YOU ,  Seung Man LIM

    IPC: H01L29/417 ,  H01L27/088 ,  H01L29/40 ,  H01L29/78 ,  H01L29/66 ,  H01L23/522 ,  G06F30/392 ,  G06F30/3953 ,  H01L29/423

    Abstract: A semiconductor device includes a first and second active pattern extending in a first direction on a substrate, a first and second gate electrode extending in a second direction to intersect the first and second active pattern, a first source/drain contact extending in the second direction and connected to a first and source/drain region of the first and second active patterns, respectively, a first source/drain via connected to the first source/drain contact, a first cell separation film extending in the second direction and crosses the first active pattern and the second active pattern, between the first source/drain contact and the second gate electrode, a first gate via connected to the second gate electrode and arranged with the first source/drain via along the first direction, and a first connection wiring which extending in the first direction and connects the first source/drain via and the first gate via.

    SEMICONDUCTOR DEVICE, LAYOUT DESIGN METHOD FOR THE SAME AND METHOD FOR FABRICATING THE SAME
    6.
    发明申请
    SEMICONDUCTOR DEVICE, LAYOUT DESIGN METHOD FOR THE SAME AND METHOD FOR FABRICATING THE SAME 有权

    公开(公告)号：US20220271133A1

    公开(公告)日：2022-08-25

    申请号：US17740829

    申请日：2022-05-10

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Ji Su YU ,  Hyeon Gyu YOU ,  Seung Man LIM

    IPC: H01L29/417 ,  H01L27/088 ,  H01L29/40 ,  H01L29/78 ,  H01L23/522 ,  G06F30/392 ,  G06F30/3953 ,  H01L29/423 ,  H01L29/66 ,  H01L23/528

    Abstract: A semiconductor device includes a first and second active pattern extending in a first direction on a substrate, a first and second gate electrode extending in a second direction to intersect the first and second active pattern, a first source/drain contact extending in the second direction and connected to a first and source/drain region of the first and second active patterns, respectively, a first source/drain via connected to the first source/drain contact, a first cell separation film extending in the second direction and crosses the first active pattern and the second active pattern, between the first source/drain contact and the second gate electrode, a first gate via connected to the second gate electrode and arranged with the first source/drain via along the first direction, and a first connection wiring which extending in the first direction and connects the first source/drain via and the first gate via.

    INTEGRATED CIRCUIT INCLUDING INTEGRATED STANDARD CELL STRUCTURE
    7.
    发明申请
    INTEGRATED CIRCUIT INCLUDING INTEGRATED STANDARD CELL STRUCTURE 有权

    公开(公告)号：US20220115406A1

    公开(公告)日：2022-04-14

    申请号：US17561887

    申请日：2021-12-24

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Hyeon Gyu YOU ,  In Gyum KIM ,  Gi Young YANG ,  Ji Su YU ,  Jin Young LIM ,  Hak Chul JUNG

    IPC: H01L27/118 ,  H01L27/02

    Abstract: An integrated circuit includes a first standard cell including a first first-type transistor, a first second-type transistor, a third second-type transistor, and a third first-type transistor, a second standard cell including a second first-type transistor, a second second-type transistor, a fourth second-type transistor and a fourth first-type transistor, a plurality of wiring layers which are disposed on the first and second standard cells and includes a first wiring layer, a second wiring layer, and a third wiring layer sequentially stacked. A source contact of the first first-type transistor and a source contact of the second first-type transistor are electrically connected through a first power rail of the plurality of wiring layers, and a source contact of the third first-type transistor and a source contact of the fourth first-type transistor are electrically connected through a second power rail of the plurality of wiring layers.

    INTEGRATED CIRCUIT INCLUDING INTEGRATED STANDARD CELL STRUCTURE
    8.
    发明申请
    INTEGRATED CIRCUIT INCLUDING INTEGRATED STANDARD CELL STRUCTURE 有权

    公开(公告)号：US20210134837A1

    公开(公告)日：2021-05-06

    申请号：US16888677

    申请日：2020-05-30

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Hyeon Gyu YOU ,  In Gyum KIM ,  Gi Young YANG ,  Ji Su YU ,  Jin Young LIM ,  Hak Chul JUNG

    IPC: H01L27/118 ,  H01L27/02

    Abstract: An integrated circuit includes a first standard cell including a first first-type transistor, a first second-type transistor, a third second-type transistor, and a third first-type transistor, a second standard cell including a second first-type transistor, a second second-type transistor, a fourth second-type transistor and a fourth first-type transistor, a plurality of wiring layers which are disposed on the first and second standard cells and includes a first wiring layer, a second wiring layer, and a third wiring layer sequentially stacked. A source contact of the first first-type transistor and a source contact of the second first-type transistor are electrically connected through a first power rail of the plurality of wiring layers, and a source contact of the third first-type transistor and a source contact of the fourth first-type transistor are electrically connected through a second power rail of the plurality of wiring layers.

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