公开(公告)号：US20240086603A1

公开(公告)日：2024-03-14

申请号：US18511605

申请日：2023-11-16

Applicant: SAMSUNG ELECTRONICS CO, LTD.

Inventor： In HUH ,  Jeong-hoon KO ,  Hyo-jin CHOI ,  Seung-ju KIM ,  Chang-wook JEONG ,  Joon-wan CHAI ,  Kwang-II PARK ,  Youn-sik PARK ,  Hyun-sun PARK ,  Young-min OH ,  Jun-haeng LEE ,  Tae-ho LEE

IPC: G06F30/33 ,  G06N3/08

CPC classification number: G06F30/33 ,  G06N3/08

Abstract: A method of reinforcement learning of a neural network device for generating a verification vector for verifying a circuit design comprising a circuit block includes inputting a test vector to the circuit block, generating one or more rewards based on a coverage corresponding to the test vector, the coverage being determined based on a state transition of the circuit block based on the test vector, and applying the one or more rewards to a reinforcement learning.

公开(公告)号：US20210174201A1

公开(公告)日：2021-06-10

申请号：US16907780

申请日：2020-06-22

Applicant: Samsung Electronics Co., Ltd.

Inventor： In HUH ,  Sanghoon MYUNG ,  Wonik JANG ,  Changwook JEONG

IPC: G06N3/08 ,  G06K9/62 ,  G06N5/04

Abstract: A computing device includes memory storing computer-executable instructions; and processing circuitry configured to execute the computer-executable instructions such that the processing circuitry is configured to operate as a machine learning generator configured to receive semiconductor process parameters, to generate semiconductor process result information from the semiconductor process parameters, and to output the generated semiconductor process result information; and operate as a machine learning discriminator configured to receive the generated semiconductor process result information from the machine learning generator and to discriminate whether the generated semiconductor process result information is true.

公开(公告)号：US20200257840A1

公开(公告)日：2020-08-13

申请号：US16788924

申请日：2020-02-12

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： In HUH ,  Jeong-hoon KO ,  Hyo-jin CHOI ,  Seung-ju KIM ,  Chang-wook JEONG ,  Joon-wan CHAI ,  Kwang-il PARK ,  Youn-sik PARK ,  Hyun-sun PARK ,  Young-min OH ,  Jun-haeng LEE ,  Tae-ho LEE

IPC: G06F30/33 ,  G06N3/08

Abstract: A device for verifying a circuit design including a first circuit block and a second circuit block includes a verification vector generator and a design verifier. The verification vector generator determines a first verification vector by performing reinforcement learning through neural network computation based on a coverage corresponding to a first test vector, the coverage being determined based on a state transition of the first circuit block generated by inputting the first test vector to the first circuit block. The design verifier performs design verification for the first circuit block by using the first verification vector.

公开(公告)号：US20230229841A1

公开(公告)日：2023-07-20

申请号：US18151051

申请日：2023-01-06

Applicant: Samsung Electronics Co., Ltd.

Inventor： Hyunjae JANG ,  Jongwon KIM ,  In HUH ,  Satbyul KIM ,  Younggu KIM ,  Yunjun NAM ,  Changwook JEONG ,  Moonhyun CHA

IPC: G06F30/392 ,  G06F30/398

CPC classification number: G06F30/392 ,  G06F30/398 ,  G06F2119/02

Abstract: A method for simulating a layout of an integrated circuit manufactured by a semiconductor process includes extracting a plurality of pattern layouts from layout data that defines the layout, generating training data by amplifying the plurality of pattern layouts and at least one parameter provided from the semiconductor process, generating sample data by sampling the training data, generating feature data including a three-dimensional array from the sample data, providing the sample data and the feature data to a simulator and a machine learning model, respectively, and training the machine learning model based on an output of the machine learning model and an output of the simulator.