公开(公告)号：US20190385695A1

公开(公告)日：2019-12-19

申请号：US16249543

申请日：2019-01-16

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Changwook JEONG ,  Sanghoon MYUNG ,  Min-Chul PARK ,  Jeonghoon KO ,  Jisu RYU ,  Hyunjae JANG ,  Hyungtae KIM ,  Yunrong LI ,  Min Chul JEON

IPC: G11C29/50 ,  G11C29/48 ,  G11C29/56 ,  G01R31/27 ,  G01R31/26 ,  G01R31/3185 ,  G01R31/30

Abstract: A fault analysis method of a semiconductor fault analysis device is provided. The fault analysis method includes: receiving measurement data measured corresponding to a semiconductor device; generating double sampling data based on the measurement data and reference data; performing a fault analysis operation with respect to the double sampling data; classifying a fault type of the semiconductor device based on a result of the fault analysis operation; and outputting information about the fault type.

公开(公告)号：US20210174201A1

公开(公告)日：2021-06-10

申请号：US16907780

申请日：2020-06-22

Applicant: Samsung Electronics Co., Ltd.

Inventor： In HUH ,  Sanghoon MYUNG ,  Wonik JANG ,  Changwook JEONG

IPC: G06N3/08 ,  G06K9/62 ,  G06N5/04

Abstract: A computing device includes memory storing computer-executable instructions; and processing circuitry configured to execute the computer-executable instructions such that the processing circuitry is configured to operate as a machine learning generator configured to receive semiconductor process parameters, to generate semiconductor process result information from the semiconductor process parameters, and to output the generated semiconductor process result information; and operate as a machine learning discriminator configured to receive the generated semiconductor process result information from the machine learning generator and to discriminate whether the generated semiconductor process result information is true.

公开(公告)号：US20210158173A1

公开(公告)日：2021-05-27

申请号：US16909132

申请日：2020-06-23

Applicant: Samsung Electronics Co., Ltd.

Inventor： Wonik JANG ,  Sanghoon MYUNG ,  Changwook JEONG ,  Sunghee LEE

IPC: G06N3/08 ,  G06N3/04

Abstract: A non-transitory computer-readable medium storing a program code including an image generation model, which when executed, causes a processor to input input data including sampling data of some of a plurality of semiconductor dies of a wafer to a generator network of the image generation model and output a wafer map indicating the plurality of semiconductor dies, and to input the wafer map output from the generator network to a discriminator network of the image generation model and discriminate the wafer map.

公开(公告)号：US20230142367A1

公开(公告)日：2023-05-11

申请号：US18153573

申请日：2023-01-12

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Sanghoon MYUNG ,  Hyunjae Jang ,  In Huh ,  Hyeon Kyun Noh ,  Min-Chul Park ,  Changwook Jeong

IPC: G06F30/27 ,  G06N3/08 ,  G06N3/10 ,  G06F30/398 ,  G06N3/044

CPC classification number: G06F30/27 ,  G06N3/08 ,  G06N3/10 ,  G06F30/398 ,  G06N3/044

Abstract: Provided is a simulation method performed by a process simulator, implemented with a recurrent neural network (RNN) including a plurality of process emulation cells, which are arranged in time series and configured to train and predict, based on a final target profile, a profile of each process step included in a semiconductor manufacturing process. The simulation method includes: receiving, at a first process emulation cell, a previous output profile provided at a previous process step, a target profile and process condition information of a current process step; and generating, at the first process emulation cell, a current output profile corresponding to the current process step, based on the target profile, the process condition information, and prior knowledge information, the prior knowledge information defining a time series causal relationship between the previous process step and the current process step.

公开(公告)号：US20210158152A1

公开(公告)日：2021-05-27

申请号：US16906038

申请日：2020-06-19

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Sanghoon MYUNG ,  Hyunjae Jang ,  In Huh ,  Hyeon Kyun Noh ,  Min-chul Park ,  Changwook Jeong

IPC: G06N3/08 ,  G06N3/04 ,  G06N3/10

Abstract: Provided is a simulation method performed by a process simulator, implemented with a recurrent neural network (RNN) including a plurality of process emulation cells, which are arranged in time series and configured to train and predict, based on a final target profile, a profile of each process step included in a semiconductor manufacturing process. The simulation method includes: receiving, at a first process emulation cell, a previous output profile provided at a previous process step, a target profile and process condition information of a current process step; and generating, at the first process emulation cell, a current output profile corresponding to the current process step, based on the target profile, the process condition information, and prior knowledge information, the prior knowledge information defining a time series causal relationship between the previous process step and the current process step.