公开(公告)号：US20220335903A1

公开(公告)日：2022-10-20

申请号：US17856182

申请日：2022-07-01

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： In-Suk KIM ,  Jungmoon KIM ,  Woo-Nyoung LEE

IPC: G09G3/3275 ,  G09G3/20 ,  G09G3/36

Abstract: An electronic device includes a first source group and a second source group, each of which includes a plurality of source channels, and a gamma block that receives first to 2i-th initial voltages (i being an integer of 1 or more), outputs first to 2i-th intermediate voltages by amplifying the first to i-th initial voltages, and outputs first to i-th gamma voltages to the first source group by buffering the first to 2i-th intermediate voltages, and a first buffer block that receives the first to 2i-th intermediate voltages from the gamma block and buffers the first to 2i-th intermediate voltages so as to be output to the second source group, and the gamma block may include a first resistor string including a plurality of resistors connected between nodes from which the first to i-th gamma voltages are output.

公开(公告)号：US20210366405A1

公开(公告)日：2021-11-25

申请号：US17108141

申请日：2020-12-01

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： In-Suk KIM ,  Jungmoon KIM ,  Woo-Nyoung LEE

IPC: G09G3/3275 ,  G09G3/3266 ,  G09G3/20 ,  G09G3/3216 ,  G09G3/36

Abstract: An electronic device includes a first source group and a second source group, each of which includes a plurality of source channels, and a gamma block that receives first to 2i-th initial voltages (i being an integer of 1 or more), outputs first to 2i-th intermediate voltages by amplifying the first to i-th initial voltages, and outputs first to i-th gamma voltages to the first source group by buffering the first to 2i-th intermediate voltages, and a first buffer block that receives the first to 2i-th intermediate voltages from the gamma block and buffers the first to 2i-th intermediate voltages so as to be output to the second source group, and the gamma block may include a first resistor string including a plurality of resistors connected between nodes from which the first to i-th gamma voltages are output.

公开(公告)号：US20130271507A1

公开(公告)日：2013-10-17

申请号：US13765752

申请日：2013-02-13

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： In-Suk KIM ,  Byung-hun HAN ,  Jae-hyuck WOO

IPC: G09G3/32

CPC classification number: G09G3/3291 ,  G09G3/3208 ,  G09G3/3225 ,  G09G2310/027 ,  G09G2320/043 ,  G09G2320/0673 ,  G09G2330/028

Abstract: A gradation voltage generator for applying a gradation voltage according to gamma characteristics of a display panel includes a reference gamma selector that receives a maximum reference voltage, a minimum reference voltage, and a first reference voltage, and selects and outputs a maximum gamma voltage and a minimum gamma voltage from among voltages between the maximum reference voltage and the minimum reference voltage, wherein when the maximum reference voltage changes, the minimum gamma voltage is compensated by a difference the changed maximum reference voltage and the first reference voltage and a gamma curve controller that receives the maximum gamma voltage and the minimum gamma voltage, and generates and outputs a plurality of gradation voltages.

公开(公告)号：US20230063319A1

公开(公告)日：2023-03-02

申请号：US17704595

申请日：2022-03-25

Applicant: Samsung Electronics Co., Ltd.

Inventor： In-Suk KIM ,  Yeonjeong LEE

IPC: G09G3/20

Abstract: Disclosed is a gamma amplifier which includes a first amplification device that receives a first input signal during a first track period in a first time period, compensates for a first offset voltage from the first input signal during a first compensation period in the first time period, and generates a first output signal during a second time period after the first time period based on a control signal, and a second amplification device that receives a second input signal during a second track period in the second time period, compensates for a second offset voltage from the second input signal during a second compensation period in the second time period, and generates a second output signal during a third time period after the second time period based on the control signal and processing circuitry configured to generate the control signal.

公开(公告)号：US20210027736A1

公开(公告)日：2021-01-28

申请号：US17036627

申请日：2020-09-29

Applicant: Samsung Electronics Co., Ltd.

Inventor： In-Suk KIM ,  Chan Bong YU

IPC: G09G3/36

Abstract: A gamma adjustment circuit includes: a first node; a second node; a first decoder to which a first voltage signal and a second voltage signal are provided and which outputs either one of the first voltage signal and the second voltage signal as a third voltage signal; an amplifier receiving the third voltage signal as a positive input and outputting a fourth voltage signal; a second decoder receiving the fourth voltage signal and outputting the provided fourth voltage signal as a fifth voltage signal to one of the first and second nodes; a third decoder connected to the first and second nodes, receives the fifth voltage signal from one of the first and second nodes, and outputs the fifth voltage signal to a negative input terminal of the amplifier as a sixth voltage signal; and a first resistor connected between the first node and the second node.

公开(公告)号：US20190295490A1

公开(公告)日：2019-09-26

申请号：US16207336

申请日：2018-12-03

Applicant: Samsung Electronics Co., Ltd.

Inventor： In-Suk KIM ,  Chan Bong YU

IPC: G09G3/36

Abstract: A gamma adjustment circuit is provided. The gamma adjustment circuit includes: a first node; a second node different from the first node; a first decoder to which a first voltage signal and a second voltage signal are provided and which outputs either one of the first voltage signal and the second voltage signal as a third voltage signal; an amplifier which receives the third voltage signal as a positive input and outputs a fourth voltage signal; a second decoder which receives the fourth voltage signal and outputs the provided fourth voltage signal as a fifth voltage signal to one of the first and second nodes; a third decoder which is connected to the first and second nodes, receives the fifth voltage signal from one of the first and second nodes, and outputs the fifth voltage signal to a negative input terminal of the amplifier as a sixth voltage signal; and a first resistor connected between the first node and the second node.

公开(公告)号：US20150222252A1

公开(公告)日：2015-08-06

申请号：US14546376

申请日：2014-11-18

Applicant: Samsung Electronics Co., Ltd.

Inventor： Hyung-Tae KIM ,  Ji-Woon JUNG ,  In-Suk KIM ,  Jong-Kon BAE ,  Jae-Hyuck WOO ,  Won-Sik KANG ,  Yang-Hyo KIM

IPC: H03K5/003 ,  H03K17/687

CPC classification number: H03K5/003 ,  G09G3/3688 ,  G09G2310/027 ,  G09G2310/0275 ,  G09G2310/0291 ,  H03F3/3022 ,  H03F3/45112 ,  H03F3/45771 ,  H03F2203/45212 ,  H03K17/687

Abstract: Provided are an output buffer circuit having an amplifier offset compensation function and a source driving circuit including the output buffer circuit. The output butler circuit may include a plurality of channel amplifiers, each of which is configured to adjust an amount of current flowing through transistors connected to at least one of a non-inverted input terminal and an inverted input terminal of a differential input unit to compensate an amplifier offset, and adjust buffer input voltage signals to generate output voltage signals.

Abstract translation: 提供具有放大器偏移补偿功能的输出缓冲电路和包括输出缓冲电路的源极驱动电路。 输出管家电路可以包括多个通道放大器，每个通道放大器被配置为调节流过连接到差分输入单元的非反相输入端子和反相输入端子中的至少一个的晶体管的电流量，以补偿 放大器偏置，并调整缓冲器输入电压信号以产生输出电压信号。

公开(公告)号：US20190156764A1

公开(公告)日：2019-05-23

申请号：US16126575

申请日：2018-09-10

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： In-Suk KIM ,  Chan-Bong YU

IPC: G09G3/3291 ,  G09G3/20

Abstract: A source driving circuit of a display device includes a plurality of unit driving circuits configured to drive a plurality of connection nodes connected to a display panel. Each unit driving circuit includes a plurality of driver circuits and output switches. The driver circuits perform analog-conversion and amplification operations on a plurality of digital data signals to generate a plurality of analog data signals. The output switches are connected in parallel between the driver circuits and a corresponding connection node among the plurality of connection nodes. The output switches transfer the plurality of analog data signals alternately to the corresponding connection node. Each one of the plurality of connection nodes may be driven by more than one of the plurality of driver circuits. The source settling time is reduced and performance of the display device is enhanced by disposing a plurality of unit driving circuits to each connection node.