公开(公告)号：US20170169756A1

公开(公告)日：2017-06-15

申请号：US15362931

申请日：2016-11-29

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Jeong-Pyo KIM ,  Jin-Hong HWANG ,  Ki-Ho KONG ,  Yang-Hyo KIM ,  Eui-Hyuk JEONG

IPC: G09G3/20

CPC classification number: G09G3/2092 ,  G09G2310/0224 ,  G09G2310/0291 ,  G09G2330/00

Abstract: A display device includes an image processor configured to invert a switch signal at a change of frames, and output, based on the switch signal, one among odd column pixel data and even column pixel data among first through (2M)-th column pixel data included in a frame data, as a half frame data, a display panel including first through M-th odd column pixels coupled to first through M-th odd column lines, respectively, and first through M-th even column pixels coupled to first through M-th even column lines, respectively, and a driving circuit including first through M-th driving units including a K-th driving unit configured to drive, based on the switch signal, one among K-th odd column pixels through a K-th odd column line and K-th even column pixels through a K-th even column line, using a K-th column pixel data included in the half frame data.

公开(公告)号：US20150222252A1

公开(公告)日：2015-08-06

申请号：US14546376

申请日：2014-11-18

Applicant: Samsung Electronics Co., Ltd.

Inventor： Hyung-Tae KIM ,  Ji-Woon JUNG ,  In-Suk KIM ,  Jong-Kon BAE ,  Jae-Hyuck WOO ,  Won-Sik KANG ,  Yang-Hyo KIM

IPC: H03K5/003 ,  H03K17/687

CPC classification number: H03K5/003 ,  G09G3/3688 ,  G09G2310/027 ,  G09G2310/0275 ,  G09G2310/0291 ,  H03F3/3022 ,  H03F3/45112 ,  H03F3/45771 ,  H03F2203/45212 ,  H03K17/687

Abstract: Provided are an output buffer circuit having an amplifier offset compensation function and a source driving circuit including the output buffer circuit. The output butler circuit may include a plurality of channel amplifiers, each of which is configured to adjust an amount of current flowing through transistors connected to at least one of a non-inverted input terminal and an inverted input terminal of a differential input unit to compensate an amplifier offset, and adjust buffer input voltage signals to generate output voltage signals.

Abstract translation: 提供具有放大器偏移补偿功能的输出缓冲电路和包括输出缓冲电路的源极驱动电路。 输出管家电路可以包括多个通道放大器，每个通道放大器被配置为调节流过连接到差分输入单元的非反相输入端子和反相输入端子中的至少一个的晶体管的电流量，以补偿 放大器偏置，并调整缓冲器输入电压信号以产生输出电压信号。

公开(公告)号：US20160343355A1

公开(公告)日：2016-11-24

申请号：US15158804

申请日：2016-05-19

Applicant: Samsung Electronics Co., Ltd.

Inventor： Yang-Hyo KIM ,  Chul-Ho KIM ,  Sun-Young KIM ,  Hak-Song KIM ,  Sang-Hoon LIM

IPC: G09G5/399 ,  G09G5/393

CPC classification number: G09G5/399 ,  G09G5/001 ,  G09G5/003 ,  G09G5/006 ,  G09G5/12 ,  G09G2310/04 ,  G09G2330/021 ,  G09G2350/00 ,  G09G2360/18

Abstract: An display driving circuit including a buffer write controller transmitting a different image frame to a first buffer or a second buffer, a buffer scan controller scanning an image frame stored in the first buffer or the second buffer on the basis of a predetermined cycle, a write signal detector controlling the buffer write controller such that a second image frame is transmitted to the second buffer after a first image frame is transmitted to the first buffer, and a scan buffer switching controller receiving an EOF (End of Frame) command indicating the completion of transmission of the first image frame to the first buffer and controlling the buffer scan controller such that the first image frame stored in the first buffer is scanned after the image frame previously stored in the second buffer is scanned.

Abstract translation: 一种显示驱动电路，包括：向第一缓冲器或第二缓冲器发送不同图像帧的缓冲写入控制器;基于预定周期扫描存储在第一缓冲器或第二缓冲器中的图像帧的缓冲器扫描控制器;写入 信号检测器控制缓冲器写入控制器，使得在将第一图像帧发送到第一缓冲器之后将第二图像帧发送到第二缓冲器，并且扫描缓冲器切换控制器接收指示完成的第二图像帧的EOF（帧结束）命令 将第一图像帧传输到第一缓冲器并控制缓冲器扫描控制器，使得在先前存储在第二缓冲器中的图像帧被扫描之后，扫描存储在第一缓冲器中的第一图像帧。