公开(公告)号：US20250167144A1

公开(公告)日：2025-05-22

申请号：US18665324

申请日：2024-05-15

Applicant: Samsung Electronics Co., Ltd.

Inventor： Junho Lee ,  JUHYEON KIM ,  SEUNGHOON YEON ,  SeungRyong Oh

IPC: H01L23/00 ,  H01L23/48 ,  H01L25/065

Abstract: A semiconductor structure may include a first redistribution line, a first redistribution via that is positioned on the first redistribution line and has a width in the horizontal direction that decreases from a bottom end of the first redistribution via to a top end of the first redistribution via, a second redistribution line that is positioned on the first redistribution via, a dielectric that covers the first redistribution line, the first redistribution via, and the second redistribution line, and a first seed metal layer that is positioned between the lower surface of the first redistribution via and the first redistribution line, between the side surface of the first redistribution via and the dielectric, and between the lower surface of the second redistribution line and the dielectric.

公开(公告)号：US20240113057A1

公开(公告)日：2024-04-04

申请号：US18231102

申请日：2023-08-07

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： JUHYEON KIM ,  YEONGSEON KIM ,  SUNKYOUNG SEO ,  CHAJEA JO

IPC: H01L23/00 ,  H01L23/48 ,  H01L23/538

CPC classification number: H01L24/08 ,  H01L23/481 ,  H01L23/5383 ,  H01L24/05 ,  H01L2224/05556 ,  H01L2224/08145

Abstract: A semiconductor package includes a first semiconductor chip stacked on a second semiconductor chip. The first semiconductor chip includes a first substrate, a first insulating layer on a lower surface of the first substrate, and a first pad exposed through the first insulating layer. The second semiconductor chip includes a second substrate, a second insulating layer on an upper surface of the second substrate contacting the first insulating layer, and a second pad exposed through the second insulating layer contacting the first pad. The first pad has an inclined side surface and a first width that increases toward the first substrate, and the second pad has an inclined side surface and a second width that increases toward the second substrate.

公开(公告)号：US20250105127A1

公开(公告)日：2025-03-27

申请号：US18659864

申请日：2024-05-09

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Dohyun KIM ,  Yeongseon KIM ,  JUHYEON KIM ,  HYOEUN KIM ,  SUNKYOUNG SEO ,  Haksun LEE

IPC: H01L23/498 ,  H01L23/00 ,  H01L23/48 ,  H01L23/528 ,  H01L23/544 ,  H01L25/10

Abstract: A semiconductor package may include a first dielectric structure, a first pad in the first dielectric structure, a first semiconductor chip provided on the first dielectric structure, and a bump electrically connected to the first pad. The first semiconductor chip includes: a first substrate; a first chip dielectric layer in contact with the first dielectric structure; and a first chip pad in contact with a top surface of the first pad. The first pad may be provided between the bump and the first chip of the first semiconductor chip. The first pad may include a first conductive layer and a second conductive layer covered by the first conductive layer. The bump may be positioned closer to the first conductive layer than to the second conductive layer.

公开(公告)号：US20250105097A1

公开(公告)日：2025-03-27

申请号：US18670378

申请日：2024-05-21

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Yeongseon KIM ,  JUHYEON KIM

IPC: H01L23/48 ,  H01L23/00 ,  H01L23/28 ,  H01L23/498 ,  H01L25/065

Abstract: A semiconductor package includes a first chip, a second chip on an active surface of the first chip, a dummy chip on the active surface of the first chip, a mold layer on the active surface of the first chip and enclosing the second chip and the dummy chip, and a conductive post vertically penetrating the mold layer proximate to the second chip and the dummy chip to be coupled to the active surface of the first chip. An active surface of the second chip and an active surface of the dummy chip may be in direct contact with the active surface of the first chip. The dummy chip may include a first via. The second chip includes a second via chip. A width of the first via is larger than a width of the second via.