公开(公告)号：US20250167144A1

公开(公告)日：2025-05-22

申请号：US18665324

申请日：2024-05-15

Applicant: Samsung Electronics Co., Ltd.

Inventor： Junho Lee ,  JUHYEON KIM ,  SEUNGHOON YEON ,  SeungRyong Oh

IPC: H01L23/00 ,  H01L23/48 ,  H01L25/065

Abstract: A semiconductor structure may include a first redistribution line, a first redistribution via that is positioned on the first redistribution line and has a width in the horizontal direction that decreases from a bottom end of the first redistribution via to a top end of the first redistribution via, a second redistribution line that is positioned on the first redistribution via, a dielectric that covers the first redistribution line, the first redistribution via, and the second redistribution line, and a first seed metal layer that is positioned between the lower surface of the first redistribution via and the first redistribution line, between the side surface of the first redistribution via and the dielectric, and between the lower surface of the second redistribution line and the dielectric.

公开(公告)号：US20240170464A1

公开(公告)日：2024-05-23

申请号：US18356325

申请日：2023-07-21

Applicant: Samsung Electronics Co., Ltd.

Inventor： Chajea Jo ,  Dohyun Kim ,  SeungRyong Oh

IPC: H01L25/16 ,  H01L23/00 ,  H01L23/31 ,  H01L23/48 ,  H01L23/498

CPC classification number: H01L25/16 ,  H01L23/3135 ,  H01L23/481 ,  H01L23/49822 ,  H01L23/49838 ,  H01L23/49894 ,  H01L24/08 ,  H01L24/16 ,  H01L24/24 ,  H01L24/73 ,  H01L2224/08148 ,  H01L2224/16227 ,  H01L2224/16238 ,  H01L2224/24225 ,  H01L2224/73209 ,  H01L2924/15174

Abstract: Disclosed is a semiconductor package including a substrate, a first semiconductor chip on the substrate and including a through via in the first semiconductor chip and a plurality of first bonding pads on an upper portion of the first semiconductor chip, a second semiconductor chip on the first semiconductor chip and including a plurality of second bonding pads on a lower portion of the second semiconductor chip, and a conductive post between a top surface of the substrate and a bottom surface of the second semiconductor chip and laterally spaced apart from the first semiconductor chip. The first bonding pads are in contact with the second bonding pads. A width in a first direction parallel to a plane defined by a bottom surface of the substrate of the second semiconductor chip is greater than a width in the first direction of the first semiconductor chip.