公开(公告)号：US20250165685A1

公开(公告)日：2025-05-22

申请号：US18952627

申请日：2024-11-19

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Byeongnoh KIM ,  Suhyun CHAE ,  Dohan KIM ,  Younghoon SON ,  Jeeyong LEE ,  Insu CHOI

IPC: G06F30/32 ,  G06N3/12

Abstract: An electronic device includes a Plackett-Burman design (PBD) execution circuit, a genetic algorithm (GA) execution circuit, and a control circuit. The PBD execution circuit is configured to generate an initial design of experiment (DOE) set including a plurality of initial cases regarding semiconductor characteristics of a memory device of an external device. The GA execution circuit is configured to convert a previous generation DOE set to a next generation DOE set. The control circuit is configured to transmit the initial DOE set to the external device, receive, from the external device, an initial characteristic evaluation, generate a starting DOE set based on the initial characteristic evaluation, and control a genetic algorithm to be performed with an experimental result of the starting DOE set as an input. Each of the plurality of initial cases corresponds to a combination of a plurality of setting values influencing the semiconductor characteristics.

公开(公告)号：US20210334444A1

公开(公告)日：2021-10-28

申请号：US17112048

申请日：2020-12-04

Applicant: Samsung Electronics Co., Ltd.

Inventor： Sooyong LEE ,  Jeeyong LEE ,  Jaeho JEONG

IPC: G06F30/392 ,  G06N20/00 ,  G06N5/04 ,  G03F7/20

Abstract: Disclosed is a method for fabricating of a semiconductor device. The method includes receiving a first layout including patterns for the fabrication of the semiconductor device, performing machine learning-based process proximity correction (PPC) based on features of the patterns of the first layout to generate a second layout, and performing optical proximity correction (OPC) on the second layout to generate a third layout.

公开(公告)号：US20240020450A1

公开(公告)日：2024-01-18

申请号：US18360209

申请日：2023-07-27

Applicant: Samsung Electronics Co., Ltd.

Inventor： Sooyong LEE ,  Jeeyong LEE ,  Jaeho JEONG

IPC: G06F30/392 ,  G06N20/00 ,  G03F7/00 ,  G06N5/04

CPC classification number: G06F30/392 ,  G06N20/00 ,  G03F7/70441 ,  G06N5/04 ,  G06F2119/18

Abstract: Disclosed is a method for fabricating of a semiconductor device. The method includes receiving a first layout including patterns for the fabrication of the semiconductor device, performing machine learning-based process proximity correction (PPC) based on features of the patterns of the first layout to generate a second layout, and performing optical proximity correction (OPC) on the second layout to generate a third layout.

公开(公告)号：US20230028712A1

公开(公告)日：2023-01-26

申请号：US17701520

申请日：2022-03-22

Applicant: Samsung Electronics Co., Ltd.

Inventor： Sooyong LEE ,  Dongho KIM ,  Sangwook KIM ,  Jungmin KIM ,  Seunghune YANG ,  Jeeyong LEE ,  Changmook YIM ,  Yangwoo HEO

IPC: G06F30/392 ,  G03F7/20

Abstract: Disclosed is an operating method of an electronic device which includes receiving a design layout for manufacturing the semiconductor device, generating a first layout by performing machine learning-based process proximity correction (PPC), generating a second layout by performing optical proximity correction (OPC), and outputting the second layout for a semiconductor process. The generating of the first layout includes generating a first after cleaning inspection (ACI) layout by executing a machine learning-based process proximity correction module on the design layout, generating a second after cleaning inspection layout by adjusting the design layout based on a difference of the first after cleaning inspection layout and the design layout and executing the process proximity correction module on the adjusted layout, and outputting the adjusted layout as the first layout, when a difference between the second after cleaning inspection layout and the design layout is smaller than or equal to a threshold value.