公开(公告)号：US20180365368A1

公开(公告)日：2018-12-20

申请号：US15933958

申请日：2018-03-23

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jung-ho DO ,  Jong-hoon JUNG ,  Ji-su YU ,  Seung-young LEE ,  Tae-joong SONG ,  Jae-boong LEE

IPC: G06F17/50

CPC classification number: G06F17/5081 ,  G06F17/5072 ,  H01L27/0207 ,  H01L27/11807

Abstract: Provided is an integrated circuit including a plurality of standard cells each including a front-end-of-line (FEOL) region and a back-end-of-line (BEOL) region on the FEOL region, the FEOL region including at least one gate line extending in a first horizontal direction. A BEOL region of a first standard cell among the plurality of standard cells includes an eaves section not overlapping an FEOL region of the first standard cell in a vertical direction, the eaves section protruding in a second horizontal direction perpendicular to the first horizontal direction.