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    DISPLAY APPARATUS AND METHOD FOR CONTROLLING THE SAME
    1.
    发明申请
    DISPLAY APPARATUS AND METHOD FOR CONTROLLING THE SAME 审中-公开
    显示装置及其控制方法

    公开(公告)号：US20160365051A1

    公开(公告)日：2016-12-15

    申请号：US15171025

    申请日：2016-06-02

    Applicant: SAMSUNG ELECTRONICS CO., LTD.

    Inventor： Jong-hoon JUNG ,  Young-mok PARK ,  Dae-sik KIM

    IPC: G09G3/36 ,  G09G3/34

    CPC classification number: G09G3/3648 ,  G09G3/3406 ,  G09G3/342 ,  G09G3/3677 ,  G09G2310/08 ,  G09G2320/0223 ,  G09G2320/0233

    Abstract: A display apparatus includes a display panel including pixels arranged at an intersection of data lines and gate lines, a source driver IC configured to be disposed on one side surface of the display panel to apply a data voltage to the data lines, a gate driver IC configured to be disposed on any one of two side surfaces which are adjacent to the one side surface of the display panel to apply a gate driving voltage to the gate lines, and a controller configured to receive feedback on a gate driving voltage applied to at least one pixel, detect a distortion of the gate driving voltage applied to the pixel based on the feedback, adjust a level of the gate driving voltage applied to the gate lines to compensate for the distortion of the gate driving voltage, and apply the adjusted gate driving voltage to the gate lines.

    Abstract translation: 显示装置包括：显示面板，包括排列在数据线和栅极线交点处的像素;源极驱动器IC，被配置为设置在显示面板的一个侧面上以对数据线施加数据电压;栅极驱动器IC 被配置为设置在与所述显示面板的所述一个侧表面相邻的两个侧表面中的任一个上，以将栅极驱动电压施加到所述栅极线;以及控制器，被配置为接收至少施加到栅极驱动电压的反馈 一个像素，基于反馈来检测施加到像素的栅极驱动电压的失真，调整施加到栅极线的栅极驱动电压的电平，以补偿栅极驱动电压的失真，并施加调节的栅极驱动 电压到栅极线。

    DISPLAY MODULE AND MULTI-DISPLAY DEVICE INCLUDING THE SAME
    5.
    发明申请
    DISPLAY MODULE AND MULTI-DISPLAY DEVICE INCLUDING THE SAME 审中-公开
    显示模块和包括其的多显示设备

    公开(公告)号：US20160197134A1

    公开(公告)日：2016-07-07

    申请号：US14854128

    申请日：2015-09-15

    Applicant: SAMSUNG ELECTRONICS CO., LTD.

    Inventor： Jong-hoon JUNG ,  Dae-sik KIM ,  Young-mok PARK

    IPC: H01L27/32 ,  H01L51/52 ,  G02F1/1345 ,  G02F1/1368 ,  G02F1/1335

    CPC classification number: H01L27/3293 ,  G02F1/133512 ,  G02F1/13452 ,  G02F1/1368 ,  G02F2201/52 ,  H01L27/3218 ,  H01L27/3251 ,  H01L51/5284

    Abstract: A display module is provided including a pixel region having a plurality of pixels and a black matrix arranged outside the pixel region. Each of the pixels is separated from adjacent pixels by a first interval, a left distance from the left edge to a first one of the plurality of pixels plus a right distance from a second one of the plurality of pixels to the right edge is a first distance, and a bottom distance from the bottom edge to a third one of the plurality of pixels plus a top distance from a fourth one of the plurality of pixels to the top edge is the first distance.

    Abstract translation: 提供一种显示模块，其包括具有多个像素的像素区域和布置在像素区域外的黑矩阵。 每个像素与相邻像素分离第一间隔，从左边缘到多个像素中的第一个像素的左距离加上从多个像素中的第二像素到右边缘的正确距离是第一 距离以及从多个像素中的底边到第三个像素的底部距离加上从多个像素中的第四个像素到顶边的顶部距离是第一距离。

    INTEGRATED CIRCUIT INCLUDING STANDARD CELL
    7.
    发明申请
    INTEGRATED CIRCUIT INCLUDING STANDARD CELL 审中-公开

    公开(公告)号：US20200294905A1

    公开(公告)日：2020-09-17

    申请号：US16886020

    申请日：2020-05-28

    Applicant: SAMSUNG ELECTRONICS CO., LTD.

    Inventor： In-gyum KIM ,  Ha-young KIM ,  Tae-joong SONG ,  Jong-hoon JUNG ,  Gi-young YANG ,  Jin-young LIM

    IPC: H01L23/50 ,  H01L29/788 ,  H01L23/528 ,  H01L27/02 ,  H01L27/118

    Abstract: A standard cell of an IC includes a cell area including a transistor configured to determine a function of the standard cell; a first dummy area and a second dummy area respectively adjacent to two sides of the cell area in a first direction; and an active area extending in the first direction across the cell area, the first dummy area, and the second dummy area. The active area includes a first active area and a second active area spaced apart from each other in a second direction perpendicular to the first direction and extend parallel to each other in the first direction. At least one of the first active area and the second active area provided in the first dummy area is biased, and at least one of the first active area and the second active area provided in the second dummy area is biased.

    INTEGRATED CIRCUIT INCLUDING STANDARD CELL
    8.
    发明申请
    INTEGRATED CIRCUIT INCLUDING STANDARD CELL 审中-公开

    公开(公告)号：US20190287891A1

    公开(公告)日：2019-09-19

    申请号：US16433092

    申请日：2019-06-06

    Applicant: SAMSUNG ELECTRONICS CO., LTD.

    Inventor： In-gyum KIM ,  Ha-young KIM ,  Tae-joong SONG ,  Jong-hoon JUNG ,  Gi-young YANG ,  Jin-young LIM

    IPC: H01L23/50 ,  H01L29/788 ,  H01L27/118 ,  H01L27/02 ,  H01L23/528

    Abstract: A standard cell of an IC includes a cell area including a transistor configured to determine a function of the standard cell; a first dummy area and a second dummy area respectively adjacent to two sides of the cell area in a first direction; and an active area extending in the first direction across the cell area, the first dummy area, and the second dummy area. The active area includes a first active area and a second active area spaced apart from each other in a second direction perpendicular to the first direction and extend parallel to each other in the first direction. At least one of the first active area and the second active area provided in the first dummy area is biased, and at least one of the first active area and the second active area provided in the second dummy area is biased.

    INTEGRATED CIRCUIT AND SEMICONDUCTOR DEVICE
    10.
    发明申请
    INTEGRATED CIRCUIT AND SEMICONDUCTOR DEVICE 审中-公开

    公开(公告)号：US20180108646A1

    公开(公告)日：2018-04-19

    申请号：US15674931

    申请日：2017-08-11

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Seung-young LEE ,  Jong-hoon JUNG ,  Myoung-ho KANG ,  Jung-ho DO

    IPC: H01L27/02 ,  G11C11/40 ,  H01L27/105 ,  H01L27/118 ,  H01L23/528

    Abstract: In one embodiment, the standard cell includes first and second active regions defining an intermediate region between the first and second active regions; and first, second and third gate lines crossing the first and second active regions and crossing the intermediate region. The first gate line is divided into an upper first gate line and a lower first gate line by a first gap insulating layer in the intermediate region, the second gate line is undivided, and the third gate line is divided into an upper third gate line and a lower third gate line by a second gap insulating layer in the intermediate region.

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