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    DEVICE FOR SUPPORTING ERROR CORRECTION CODE AND TEST METHOD THEREOF
    5.
    发明申请
    DEVICE FOR SUPPORTING ERROR CORRECTION CODE AND TEST METHOD THEREOF 审中-公开

    公开(公告)号：US20190088349A1

    公开(公告)日：2019-03-21

    申请号：US16135325

    申请日：2018-09-19

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Suk-soo PYO ,  Hyun-taek JUNG ,  Tae-joong SONG

    IPC: G11C29/42 ,  G06F11/10

    CPC classification number: G11C29/42 ,  G06F11/1044 ,  G06F11/2215 ,  G11C29/36 ,  G11C29/46 ,  G11C2029/0403

    Abstract: A device for supporting a test mode for memory testing according to an example embodiment of the inventive concepts may include a memory configured to receive and store writing data and output reading data from the stored writing data; an error correction code (ECC) engine configured to generate the writing data by encoding input data and to generate output data by correcting error bits of N bits or less included in receiving data when N is a positive integer; and an error insertion circuit configured to provide the reading data to the ECC engine as the receiving data in a normal mode and to provide data obtained by inverting at least one bit of less than N bits of the reading data to the ECC engine as the receiving data in the test mode.

    INTEGRATED CIRCUIT AND SEMICONDUCTOR DEVICE
    6.
    发明申请
    INTEGRATED CIRCUIT AND SEMICONDUCTOR DEVICE 有权

    公开(公告)号：US20170133380A1

    公开(公告)日：2017-05-11

    申请号：US15409523

    申请日：2017-01-18

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Ha-young KIM ,  Sung-we CHO ,  Tae-joong SONG ,  Sang-hoon BAEK

    IPC: H01L27/092 ,  G06F17/50 ,  H01L27/02 ,  H01L23/522 ,  H01L23/528

    CPC classification number: H01L27/0924 ,  G06F17/5077 ,  H01L23/5226 ,  H01L23/528 ,  H01L23/5286 ,  H01L27/0207 ,  H01L27/092

    Abstract: An embodiment includes an integrated circuit comprising a standard cell, the standard cell comprising: first and second active regions having different conductivity types and extending in a first direction; first, second, and third conductive lines extending over the first and second active regions in a second direction substantially perpendicular to the first direction, and disposed parallel to each other; and a cutting layer extending in the first direction between the first and second active regions and separating the first conductive line into a first upper conductive line and a first lower conductive line, the second conductive line into a second upper conductive line and a second lower conductive line, and the third conductive line into a third upper conductive line and a third lower conductive line; wherein: the first upper conductive line and the third lower conductive line are electrically connected together; and the second upper conductive line and the second lower conductive line are electrically connected together.

    INTEGRATED CIRCUIT INCLUDING STANDARD CELL
    7.
    发明申请
    INTEGRATED CIRCUIT INCLUDING STANDARD CELL 审中-公开

    公开(公告)号：US20200294905A1

    公开(公告)日：2020-09-17

    申请号：US16886020

    申请日：2020-05-28

    Applicant: SAMSUNG ELECTRONICS CO., LTD.

    Inventor： In-gyum KIM ,  Ha-young KIM ,  Tae-joong SONG ,  Jong-hoon JUNG ,  Gi-young YANG ,  Jin-young LIM

    IPC: H01L23/50 ,  H01L29/788 ,  H01L23/528 ,  H01L27/02 ,  H01L27/118

    Abstract: A standard cell of an IC includes a cell area including a transistor configured to determine a function of the standard cell; a first dummy area and a second dummy area respectively adjacent to two sides of the cell area in a first direction; and an active area extending in the first direction across the cell area, the first dummy area, and the second dummy area. The active area includes a first active area and a second active area spaced apart from each other in a second direction perpendicular to the first direction and extend parallel to each other in the first direction. At least one of the first active area and the second active area provided in the first dummy area is biased, and at least one of the first active area and the second active area provided in the second dummy area is biased.

    INTEGRATED CIRCUIT INCLUDING STANDARD CELL
    8.
    发明申请
    INTEGRATED CIRCUIT INCLUDING STANDARD CELL 审中-公开

    公开(公告)号：US20190287891A1

    公开(公告)日：2019-09-19

    申请号：US16433092

    申请日：2019-06-06

    Applicant: SAMSUNG ELECTRONICS CO., LTD.

    Inventor： In-gyum KIM ,  Ha-young KIM ,  Tae-joong SONG ,  Jong-hoon JUNG ,  Gi-young YANG ,  Jin-young LIM

    IPC: H01L23/50 ,  H01L29/788 ,  H01L27/118 ,  H01L27/02 ,  H01L23/528

    Abstract: A standard cell of an IC includes a cell area including a transistor configured to determine a function of the standard cell; a first dummy area and a second dummy area respectively adjacent to two sides of the cell area in a first direction; and an active area extending in the first direction across the cell area, the first dummy area, and the second dummy area. The active area includes a first active area and a second active area spaced apart from each other in a second direction perpendicular to the first direction and extend parallel to each other in the first direction. At least one of the first active area and the second active area provided in the first dummy area is biased, and at least one of the first active area and the second active area provided in the second dummy area is biased.

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