公开(公告)号：US20250016990A1

公开(公告)日：2025-01-09

申请号：US18656670

申请日：2024-05-07

Applicant: Samsung Electronics Co., Ltd.

Inventor： Choonghyun LEE ,  Kanguk KIM ,  Jooncheol KIM ,  Jina KIM

IPC: H10B12/00

Abstract: A semiconductor device is provided. The semiconductor device includes a first bit line crossing a memory cell array region in a first direction and extending into an extension region adjacent to the memory cell array region, a second bit line crossing the memory cell array region in the first direction and extending into the extension region, and adjacent to the first bit line, an insulating pattern within the extension region and contacting an end portion of the second bit line in the first direction, and an insulating spacer within the extension region and contacting an end portion of the first bit line in the first direction, the insulating spacer being different from the insulating pattern.

公开(公告)号：US20140231892A1

公开(公告)日：2014-08-21

申请号：US14101631

申请日：2013-12-10

Applicant: Samsung Electronics Co., Ltd.

Inventor： Bo-Young SONG ,  Cheol-Ju YUN ,  Seung-Hee KO ,  Jina KIM ,  Hyun-Gi KIM ,  Chae-Ho LIM

IPC: H01L23/522

CPC classification number: H01L21/7682 ,  H01L21/76831 ,  H01L21/76897 ,  H01L27/10814 ,  H01L27/10823 ,  H01L27/10855 ,  H01L27/10885 ,  H01L27/10888 ,  H01L27/10891

Abstract: First dopant regions and second dopant regions are provided at both sides of the gate structures. Conductive lines cross over the gate structures and are connected to the first dopant regions. Each of the conductive lines includes a conductive pattern and a capping pattern disposed on the conductive pattern. Contact structures are provided between the conductive lines and are connected to the second dopant regions. Each of the contact structures includes a lower contact pattern disposed on the second dopant region and an upper contact pattern disposed on the lower contact pattern. A bottom surface of the upper contact pattern is lower than a top surface of the conductive pattern.

Abstract translation: 第一掺杂区域和第二掺杂剂区域设置在栅极结构的两侧。 导电线在栅极结构上交叉并连接到第一掺杂区。 每个导线包括导电图案和设置在导电图案上的封盖图案。 在导线之间提供接触结构，并连接到第二掺杂剂区域。 每个接触结构包括设置在第二掺杂剂区域上的下接触图案和设置在下接触图案上的上接触图案。 上触点图案的底表面低于导电图案的顶表面。