公开(公告)号：US20220122986A1

公开(公告)日：2022-04-21

申请号：US17398136

申请日：2021-08-10

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Sukhwa JANG ,  Kanguk KIM ,  Hyunsuk NOH ,  Yeongshin PARK ,  Sangkyu SUN ,  Sunyoung LEE ,  Sohyang LEE ,  Hongjun LEE ,  Hosun JUNG ,  Jeongmin JIN ,  Jeonghee CHOI ,  Jinseo CHOI ,  Cera HONG

IPC: H01L27/108

Abstract: A method of manufacturing a semiconductor device includes forming a lower structure including a plurality of transistors, forming a conductive layer on the lower structure, forming first preliminary pad mask patterns and wiring mask patterns on the conductive layer, forming pad mask patterns by patterning the first preliminary pad mask patterns while protecting the wiring mask patterns, and etching the conductive layer using the pad mask patterns and the wiring mask patterns as an etching mask to form pad patterns and wiring patterns.

公开(公告)号：US20250016990A1

公开(公告)日：2025-01-09

申请号：US18656670

申请日：2024-05-07

Applicant: Samsung Electronics Co., Ltd.

Inventor： Choonghyun LEE ,  Kanguk KIM ,  Jooncheol KIM ,  Jina KIM

IPC: H10B12/00

Abstract: A semiconductor device is provided. The semiconductor device includes a first bit line crossing a memory cell array region in a first direction and extending into an extension region adjacent to the memory cell array region, a second bit line crossing the memory cell array region in the first direction and extending into the extension region, and adjacent to the first bit line, an insulating pattern within the extension region and contacting an end portion of the second bit line in the first direction, and an insulating spacer within the extension region and contacting an end portion of the first bit line in the first direction, the insulating spacer being different from the insulating pattern.

公开(公告)号：US20240381616A1

公开(公告)日：2024-11-14

申请号：US18636744

申请日：2024-04-16

Applicant: Samsung Electronics Co., Ltd.

Inventor： Seongkeun CHO ,  Suhwan HWANG ,  Kanguk KIM ,  Yihwan KIM ,  Jihoon KIM ,  Jinhyung PARK ,  Hyunsu SHIN ,  Taemin EARMME ,  Sungwook JUNG

IPC: H10B12/00

Abstract: A method may include forming a first gate structure on a first region of a substrate, forming a bit line structure on the first gate structure, forming a preliminary contact plug layer including amorphous silicon on the substrate, forming a reflective layer structure on the preliminary contact plug layer, forming a contact plug layer from the preliminary contact plug layer, and forming a capacitor on the contact plug layer. The reflective layer structure may include first and second reflective layers. A refractive index of the second reflective layer may be being greater than that of the first reflective layer. Portions of the second reflective layer may have different thicknesses on first and second regions of the substrate. The forming the contact plug layer may include performing a melting laser annealing (MLA) process on the reflective layer structure to convert the amorphous silicon of the preliminary contact plug layer into polysilicon.