公开(公告)号：US20240284664A1

公开(公告)日：2024-08-22

申请号：US18462677

申请日：2023-09-07

Applicant: Samsung Electronics Co., Ltd.

Inventor： Sungeun Kim ,  Jinyeong Kim ,  Sungyeon Ryu ,  Hyeonok Jung ,  Sei-Ryung Choi

IPC: H10B12/00

CPC classification number: H10B12/50 ,  H10B12/315 ,  H10B12/482 ,  H10B12/488

Abstract: A semiconductor device includes peripheral active patterns on a substrate, first and second peripheral trench regions adjacent the peripheral active patterns, a first isolation liner on inner surfaces of the first and second peripheral trench regions, a second isolation liner on the first isolation liner in the first and second peripheral trench regions, and a device isolation layer on the second isolation liner in the first and second peripheral trench regions. The device isolation layer includes a seam therein in the second peripheral trench region. A width of the first peripheral trench region is greater than a width of the second peripheral trench region at a first height corresponding to top surfaces of the peripheral active patterns with respect to the substrate.