公开(公告)号：US12213256B2

公开(公告)日：2025-01-28

申请号：US17591734

申请日：2022-02-03

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Junghwa Kim ,  Junso Pak ,  Heeseok Lee ,  Moonseob Jeong ,  Jisoo Hwang

IPC: H01L23/498 ,  H01L23/00 ,  H01L23/48 ,  H01L23/538 ,  H05K1/02 ,  H05K1/18 ,  H01L25/065

Abstract: A semiconductor package including a circuit board including a first wiring region, a die mounting region surrounding the first wiring region, and a second wiring region surrounding the die mounting region; a plurality of wiring balls on the first wiring region and the second wiring region and spaced apart from one another, the plurality of wiring balls including a plurality of first wiring balls on the first wiring region and a plurality of second wiring balls on the second wiring region; a die on the die mounting region, the die including a plurality of unit chips spaced apart from one another, and a die-through region corresponding to the first wiring region and exposing the first wiring balls; and a plurality of die balls on the die and the die mounting region, the plurality of die balls being spaced apart from one another and electrically coupled to the circuit board.

公开(公告)号：US11830813B2

公开(公告)日：2023-11-28

申请号：US17374143

申请日：2021-07-13

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jisoo Hwang ,  Chunguan Kim ,  Heeseok Lee ,  Kyoungkuk Chae

IPC: H01L23/528 ,  H01L23/00 ,  H01L23/498 ,  H01L23/538 ,  H01L23/522 ,  H01L25/065

CPC classification number: H01L23/5286 ,  H01L23/49816 ,  H01L23/49822 ,  H01L23/49833 ,  H01L23/49838 ,  H01L23/5221 ,  H01L23/5385 ,  H01L23/5386 ,  H01L24/16 ,  H01L24/17 ,  H01L25/0655 ,  H01L2224/16235 ,  H01L2224/17134 ,  H01L2924/1427 ,  H01L2924/1432

Abstract: A semiconductor chip includes a first core region including a first core and a first power line configured to provide a first voltage to the first core, a second core region including a second core and a second power line configured to provide the first voltage to the second core, a cache region between the first core region and the second core region, the cache region including a cache and a third power line providing a second voltage to the cache, and arranged between the first core region and the second core region; and a first power connection line connecting the first power line to the second power line and arranged in the cache region.