公开(公告)号：US20240355792A1

公开(公告)日：2024-10-24

申请号：US18137360

申请日：2023-04-20

申请人： Intel Corporation

发明人： Poh Boon KHOO ,  Jiun Hann SIR ,  Eng Huat GOH ,  Hooi San LAM ,  Hazwani JAFFAR

IPC分类号： H01L25/10 ,  H01L23/00 ,  H01L23/498 ,  H01L23/538 ,  H10B80/00

CPC分类号： H01L25/105 ,  H01L23/49816 ,  H01L23/49833 ,  H01L23/5385 ,  H01L23/5386 ,  H01L24/16 ,  H01L24/32 ,  H01L24/48 ,  H01L24/73 ,  H10B80/00 ,  H01L23/49838 ,  H01L2224/16225 ,  H01L2224/32225 ,  H01L2224/48225 ,  H01L2224/73204 ,  H01L2924/1427 ,  H01L2924/1431 ,  H01L2924/1436

摘要： Embodiments disclosed herein include electronic packages. In an example, an electronic package includes a package substrate. A die is coupled to the package substrate. The electronic package also includes a memory stack. The memory stack includes a die stack structure coupled to a substrate. The substrate is coupled to and is extending laterally beyond the package substrate. The die stack structure includes a stack of dies and through vias in a mold layer. The die stack structure is laterally spaced apart from the package substrate.

公开(公告)号：US20240274549A1

公开(公告)日：2024-08-15

申请号：US18169788

申请日：2023-02-15

申请人： Advanced Micro Devices, Inc. ,  ATI Technologies ULC

发明人： Alexander Helmut Pfeiffenberger ,  Robert Grant Spurney ,  Sriranga Sai Boyapati

IPC分类号： H01L23/64 ,  H01F17/00 ,  H01F17/04 ,  H01L23/14 ,  H01L23/498 ,  H01L25/065

CPC分类号： H01L23/645 ,  H01F17/0013 ,  H01F17/04 ,  H01L23/145 ,  H01L23/49822 ,  H01L23/49838 ,  H01L25/0655 ,  H01F2017/002 ,  H01L24/16 ,  H01L24/32 ,  H01L24/73 ,  H01L2224/16227 ,  H01L2224/16237 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2924/1427 ,  H01L2924/1432 ,  H01L2924/1433 ,  H01L2924/14335

摘要： An apparatus and method for efficient power management of multiple integrated circuits. An apparatus includes an integrated circuit and a package substrate that includes an embedded inductor. The package substrate includes a glass-reinforced epoxy laminate material. The embedded inductor is formed within a cavity of the package substrate, and includes two negatively coupled inductors connected in a parallel combination. The embedded inductor receives an output voltage generated by a voltage regulator, and conveys this output voltage to a power supply input pin of the integrated circuit. Each of the two negatively coupled inductors utilizes a ferrite core. During a transient voltage condition of the output voltage generated by the voltage regulator, the embedded inductor provides an inductance that is less than an inductance it provides for a steady-state voltage condition of the output voltage generated by the voltage regulator.

公开(公告)号：US20240162192A1

公开(公告)日：2024-05-16

申请号：US17987823

申请日：2022-11-15

申请人： International Business Machines Corporation

发明人： Arvind Kumar ,  Todd Edward Takken ,  John W Golz ,  Joshua M. Rubin

IPC分类号： H01L25/065 ,  H01L23/00 ,  H01L25/00

CPC分类号： H01L25/0657 ,  H01L24/16 ,  H01L24/17 ,  H01L25/0652 ,  H01L25/50 ,  H01L2224/16146 ,  H01L2224/16221 ,  H01L2224/17133 ,  H01L2224/17177 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06541 ,  H01L2225/06589 ,  H01L2924/14252 ,  H01L2924/1426 ,  H01L2924/1427 ,  H01L2924/1431 ,  H01L2924/1441 ,  H01L2924/1443 ,  H01L2924/1444 ,  H01L2924/30205

摘要： A semiconductor module includes a first semiconductor die, which comprises (i) a power support structure and (ii) a first cache region; and a second semiconductor die, which is mounted on top of the first semiconductor die and comprises (i) a logic core, which overlies and is electrically connected to the power support structure, and (ii) a second cache region, which overlies and is electrically connected to the first cache region.

公开(公告)号：US11830813B2

公开(公告)日：2023-11-28

申请号：US17374143

申请日：2021-07-13

申请人： Samsung Electronics Co., Ltd.

发明人： Jisoo Hwang ,  Chunguan Kim ,  Heeseok Lee ,  Kyoungkuk Chae

IPC分类号： H01L23/528 ,  H01L23/00 ,  H01L23/498 ,  H01L23/538 ,  H01L23/522 ,  H01L25/065

CPC分类号： H01L23/5286 ,  H01L23/49816 ,  H01L23/49822 ,  H01L23/49833 ,  H01L23/49838 ,  H01L23/5221 ,  H01L23/5385 ,  H01L23/5386 ,  H01L24/16 ,  H01L24/17 ,  H01L25/0655 ,  H01L2224/16235 ,  H01L2224/17134 ,  H01L2924/1427 ,  H01L2924/1432

摘要： A semiconductor chip includes a first core region including a first core and a first power line configured to provide a first voltage to the first core, a second core region including a second core and a second power line configured to provide the first voltage to the second core, a cache region between the first core region and the second core region, the cache region including a cache and a third power line providing a second voltage to the cache, and arranged between the first core region and the second core region; and a first power connection line connecting the first power line to the second power line and arranged in the cache region.

公开(公告)号：US20230307405A1

公开(公告)日：2023-09-28

申请号：US17656539

申请日：2022-03-25

申请人： Advanced Micro Devices, Inc.

发明人： Lei Fu ,  Raja Swaminathan ,  Brett P. Wilkerson

IPC分类号： H01L23/00

CPC分类号： H01L24/24 ,  H01L24/19 ,  H01L24/20 ,  H01L24/25 ,  H01L24/16 ,  H01L24/73 ,  H01L2924/37001 ,  H01L2924/1434 ,  H01L2924/1431 ,  H01L2924/1433 ,  H01L2924/1427 ,  H01L2924/14252 ,  H01L2224/215 ,  H01L2224/24137 ,  H01L2224/24101 ,  H01L2224/25175 ,  H01L2224/73209 ,  H01L2224/16137 ,  H01L25/0655

摘要： An electronic device can include a first die, a second die, and an interconnect. The first die or the second die has a principal function as a power module or a memory. The first die includes a first bond pad, and the second die includes a second bond pad. The device sides of the first and second dies are along the same sides as the first and second bond pads. In an embodiment, the first die and the second die are in a chip first, die face-up configuration. The first and the second bond pads are electrically connected along a first solderless connection that includes the interconnect. In another embodiment, each material within the electrical connection between the first and the second bond pads has a flow point or melting point temperature of at least 300° C.

公开(公告)号：US20230261037A1

公开(公告)日：2023-08-17

申请号：US18306222

申请日：2023-04-24

申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

发明人： Wen-Shiang Liao ,  Chih-Hang Tung

IPC分类号： H01L23/31 ,  H01L23/498 ,  H01F27/24 ,  H01F27/28 ,  H01L23/00 ,  H01L21/48 ,  H01L21/56 ,  H01L21/683 ,  H01F41/04

CPC分类号： H01L28/10 ,  H01L23/3128 ,  H01L23/49838 ,  H01F27/24 ,  H01F27/2804 ,  H01L23/49827 ,  H01L24/19 ,  H01L21/486 ,  H01L21/565 ,  H01L21/568 ,  H01L21/561 ,  H01L21/4857 ,  H01L21/6835 ,  H01L24/97 ,  H01F41/041 ,  H01L24/20 ,  H01L2924/19042 ,  H01L2224/95001 ,  H01F2027/2809 ,  H01L2224/211 ,  H01L2224/221 ,  H01L2924/1427

摘要： A package includes a first redistribution structure, a second redistribution structure, an inductor, a permalloy core, and a die. The second redistribution structure is over the first redistribution structure. The inductor includes a first portion, a second portion, and a third portion. The first portion is embedded in the first redistribution structure, the third portion is embedded in the second redistribution structure, and the second portion connects the first and third portions of the inductor. The permalloy core is located between the first and third portions of the inductor. The die is disposed adjacent to the second portion of the inductor.

公开(公告)号：US11652062B2

公开(公告)日：2023-05-16

申请号：US16706563

申请日：2019-12-06

申请人： FARADAY SEMI, INC.

发明人： Parviz Parto

IPC分类号： H01L23/538 ,  H01L23/64 ,  H01L23/00 ,  H01L49/02 ,  H02M3/158 ,  G06F1/3287 ,  H01L21/48 ,  H01L23/498 ,  H02M1/08 ,  H02M1/00

CPC分类号： H01L23/5389 ,  G06F1/3287 ,  H01L21/4853 ,  H01L21/4857 ,  H01L23/49822 ,  H01L23/5383 ,  H01L23/5385 ,  H01L23/645 ,  H01L24/19 ,  H01L24/20 ,  H01L28/10 ,  H02M3/158 ,  H02M3/1584 ,  H01L2224/04105 ,  H01L2224/16227 ,  H01L2224/214 ,  H01L2224/73267 ,  H01L2924/00014 ,  H01L2924/1033 ,  H01L2924/10253 ,  H01L2924/13091 ,  H01L2924/1427 ,  H01L2924/15192 ,  H01L2924/15311 ,  H01L2924/19041 ,  H01L2924/19042 ,  H01L2924/19104 ,  H02M1/007 ,  H02M1/08 ,  H05K2201/10378

摘要： One or more chip-embedded integrated voltage regulators (“CEIVR's”) are configured to provide power to a circuit or chip such as a CPU or GPU and meet power delivery specifications. The CEIVR's, circuit or chip, and power delivery pathways can be included within the same package. The CEIVR's can be separate from the circuit or chip.

公开(公告)号：US20180012879A1

公开(公告)日：2018-01-11

申请号：US15205702

申请日：2016-07-08

申请人： Cisco Technology, Inc.

发明人： Paul L. Mantiply ,  Straty Argyrakis

IPC分类号： H01L25/18 ,  H05K1/18 ,  H01L23/538 ,  H05K3/34 ,  H01L25/00 ,  H01L23/367 ,  H02M3/158 ,  H05K1/02 ,  H05K1/11 ,  H01L23/498 ,  H01L25/16 ,  H01L23/00

CPC分类号： H01L25/18 ,  H01L23/3675 ,  H01L23/49827 ,  H01L23/5383 ,  H01L23/5384 ,  H01L23/5389 ,  H01L24/17 ,  H01L25/16 ,  H01L25/50 ,  H01L2924/10253 ,  H01L2924/10329 ,  H01L2924/1033 ,  H01L2924/1306 ,  H01L2924/1426 ,  H01L2924/1427 ,  H01L2924/1433 ,  H01L2924/15311 ,  H01L2924/19041 ,  H01L2924/19042 ,  H01L2924/19102 ,  H02M3/158 ,  H05K1/0204 ,  H05K1/0262 ,  H05K1/0298 ,  H05K1/115 ,  H05K1/181 ,  H05K1/185 ,  H05K3/341 ,  H05K3/3436 ,  H05K2201/10015 ,  H05K2201/1003 ,  H05K2201/10166 ,  H05K2201/10378 ,  H05K2201/10545 ,  H05K2201/10734

摘要： Presented herein is a method and apparatus for enhanced power distribution to application specific integrated circuits (ASICs). The apparatus includes a substrate, an ASIC, and a voltage regulator module. The substrate includes a first side, a second side, and a vertical interconnect access (via) extending between the first side and the second side. The ASIC is mounted on the first side of the substrate in alignment with the via. The voltage regulator module is mounted on the second side of the substrate in alignment with the via so that the voltage regulator module is electrically coupled to the ASIC through the via.

公开(公告)号：US09847323B1

公开(公告)日：2017-12-19

申请号：US14830372

申请日：2015-08-19

申请人： Xilinx, Inc.

发明人： Austin H. Lesea

IPC分类号： H05K7/10 ,  H05K7/12 ,  H01L25/18 ,  G06F17/50 ,  H01L23/498 ,  H01L23/50 ,  H01L23/00 ,  H05K1/18

CPC分类号： H01L25/18 ,  G06F17/5054 ,  H01L23/49816 ,  H01L23/49822 ,  H01L23/49894 ,  H01L23/50 ,  H01L24/17 ,  H01L2224/16227 ,  H01L2924/1427 ,  H01L2924/1431 ,  H05K1/0262

摘要： In an example, an IC package includes a package substrate including a plurality of bumps configured for coupling to a printed circuit board, the package substrate including a core disposed between a plurality of top-side conductive layers and a plurality of bottom-side conductive layers. The IC package further includes an IC die coupled to the package substrate and disposed on top of the plurality of top-side conductive layers. The IC die further includes a voltage regulator IC die disposed on the package substrate adjacent to the IC die, the voltage regulator IC die being coupled to the IC die using two of four top-most layers of the plurality of top-side conductive layers nearest the IC die.

公开(公告)号：US09831148B2

公开(公告)日：2017-11-28

申请号：US15169857

申请日：2016-06-01

申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

发明人： Chen-Hua Yu ,  Chih-Yuan Chang ,  Chuei-Tang Wang ,  Jeng-Shien Hsieh

IPC分类号： H01L23/52 ,  H01L23/31 ,  H01L21/56 ,  H01L23/48 ,  H01L23/00 ,  H01L21/54

CPC分类号： H01L24/98 ,  H01L21/561 ,  H01L21/568 ,  H01L23/3128 ,  H01L23/3675 ,  H01L23/481 ,  H01L23/5389 ,  H01L24/02 ,  H01L24/03 ,  H01L24/16 ,  H01L24/97 ,  H01L2224/04105 ,  H01L2224/12105 ,  H01L2224/18 ,  H01L2224/97 ,  H01L2924/1427

摘要： A method includes adhering a voltage regulator die over a carrier through a die-attach film, with the die-attach film being in the voltage regulator die and encircles metal pillars of the voltage regulator die, encapsulating the voltage regulator die in an encapsulating material, and planarizing the encapsulating material. A back portion of the voltage regulator die is removed to expose a through-via in a semiconductor substrate of the voltage regulator die. The method further includes forming first redistribution lines over the encapsulating material and electrically coupled to the through-via, replacing the die-attach film with a dielectric material, forming second redistribution lines on an opposite side of encapsulating material than the first redistribution lines, and bonding an additional device die to the second redistribution lines. The voltage regulator die is electrically coupled to the additional device die.