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    Package substrate and semiconductor package having the same
    2.
    发明授权
    Package substrate and semiconductor package having the same 有权
    封装衬底和具有相同的封装衬底和半导体封装

    公开(公告)号：US09030838B2

    公开(公告)日：2015-05-12

    申请号：US14147114

    申请日：2014-01-03

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Se-Ho You ,  Heeseok Lee ,  Chiyoung Lee ,  Yun-Hee Lee

    IPC: H05K7/10 ,  H05K7/12 ,  H05K1/18 ,  H05K1/11 ,  H01L23/13 ,  H01L23/498

    CPC classification number: H05K1/183 ,  H01L23/13 ,  H01L23/49816 ,  H01L2224/48227 ,  H01L2225/107 ,  H01L2924/1515 ,  H01L2924/15311 ,  H05K1/11 ,  H05K1/18 ,  H05K1/181 ,  Y02P70/611

    Abstract: Provided is a package substrate and a semiconductor package. The package substrate includes a main body having an upper surface and a lower surface opposite to the upper surface, a plurality of external terminals attached to the lower surface, and a plurality of grooves formed in regions of the lower surface to which the plurality of external terminals is not attached. The semiconductor package includes a package substrate, a semiconductor chip mounted on the upper surface of the semiconductor substrate, and a board providing a region mounted with the package substrate and being mounted with a plurality of mounting elements which are vertically aligned with the plurality of grooves and are inserted into the plurality of grooves.

    Abstract translation: 提供了封装基板和半导体封装。 封装基板包括具有上表面和与上表面相对的下表面的主体，附接到下表面的多个外部端子，以及形成在下表面的多个外部区域中的多个凹槽 端子未连接。 半导体封装包括封装衬底，安装在半导体衬底的上表面上的半导体芯片，以及提供安装有封装衬底的区域的板，并且安装有与多个沟槽垂直对准的多个安装元件 并插入到多个槽中。

    WIRING BOARDS AND SEMICONDUCTOR MODULES INCLUDING THE SAME
    3.
    发明申请
    WIRING BOARDS AND SEMICONDUCTOR MODULES INCLUDING THE SAME 有权
    接线板和包括其的半导体模块

    公开(公告)号：US20130221485A1

    公开(公告)日：2013-08-29

    申请号：US13734322

    申请日：2013-01-04

    Applicant: SAMSUNG ELECTRONICS CO., LTD.

    Inventor： YONGHOON KIM ,  Seung Hwan Kim ,  Heeseok Lee

    IPC: H05K1/18

    CPC classification number: H05K1/185 ,  H01L28/40 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2924/15311 ,  H01L2924/19105 ,  H05K3/4608 ,  H05K2201/0979 ,  H05K2201/10015

    Abstract: A wiring board includes a metal core including a first surface and a second surface facing each other and a first portion and a second portion disposed on the first and second surfaces, respectively. The first and second portions each include a plurality of insulating layers and a plurality of wiring layers stacked in an alternating manner. At least one capacitor is disposed in at least one interior region. The at least one capacitor includes first and second electrodes. The at least one interior region exposes a portion of the metal core and a portion of at least one of the first and second portions adjacent to the metal core and at least one first via electrically connects one of the wiring layers of the first portion with the first and second electrodes.

    Abstract translation: 布线板包括金属芯，该金属芯包括彼此面对的第一表面和第二表面，以及分别设置在第一表面和第二表面上的第一部分和第二部分。 第一和第二部分各自包括交替堆叠的多个绝缘层和多个布线层。 至少一个电容器设置在至少一个内部区域中。 所述至少一个电容器包括第一和第二电极。 所述至少一个内部区域暴露所述金属芯的一部分，并且所述第一和第二部分中的至少一个的一部分与所述金属芯相邻，并且至少一个第一通孔将所述第一部分的所述布线层中的一个与 第一和第二电极。

    Semiconductor package including dual stiffener
    5.
    发明授权
    Semiconductor package including dual stiffener 有权

    公开(公告)号：US11908758B2

    公开(公告)日：2024-02-20

    申请号：US17550284

    申请日：2021-12-14

    Applicant: SAMSUNG ELECTRONICS CO., LTD.

    Inventor： Heungkyu Kwon ,  Junso Pak ,  Heeseok Lee

    IPC: H01L23/16 ,  H01L23/053 ,  H01L23/31

    CPC classification number: H01L23/16 ,  H01L23/053 ,  H01L23/31

    Abstract: A semiconductor package includes; a dual stiffener including an upper stiffener and a lower stiffener, an upper package including an upper package substrate, a semiconductor chip centrally mounted on an upper surface of the upper package substrate, and the upper stiffener disposed along an outer edge of the upper package substrate, and a lower package substrate that centrally mounts the upper package and includes the lower stiffener disposed on an upper surface of the lower package substrate to surround the upper package substrate.

    Semiconductor package including composite molding structure
    8.
    发明授权
    Semiconductor package including composite molding structure 有权

    公开(公告)号：US11373933B2

    公开(公告)日：2022-06-28

    申请号：US17016115

    申请日：2020-09-09

    Applicant: SAMSUNG ELECTRONICS CO., LTD.

    Inventor： Heeseok Lee ,  Yunhyeok Im

    IPC: H01L23/48 ,  H01L23/498 ,  H01L23/31 ,  H01L25/10 ,  H01L23/40

    Abstract: A semiconductor package includes; a lower semiconductor chip mounted on a lower package substrate, an interposer on the lower package substrate and including an opening, connection terminals spaced apart from and at least partially surrounding the lower semiconductor chip and extending between the lower package substrate and the interposer, a first molding member including a first material and covering at least a portion of a top surface of the lower semiconductor chip and at least portions of edge surfaces of the lower semiconductor chip, wherein the first molding member includes a protrusion that extends upward from the opening to cover at least portions of a top surface of the interposer proximate to the opening, and a second molding member including a second material, at least partially surrounding the first molding member, and covering side surfaces of the first molding member and the connection terminals, wherein the first material has thermal conductivity greater than the second material.

    Semiconductor package including composite molding structure
    10.
    发明授权
    Semiconductor package including composite molding structure 有权

    公开(公告)号：US11908774B2

    公开(公告)日：2024-02-20

    申请号：US17850504

    申请日：2022-06-27

    Applicant: SAMSUNG ELECTRONICS CO., LTD.

    Inventor： Heeseok Lee ,  Yunhyeok Im

    IPC: H01L23/48 ,  H01L23/498 ,  H01L23/31 ,  H01L25/10 ,  H01L23/40

    CPC classification number: H01L23/481 ,  H01L23/3135 ,  H01L23/498 ,  H01L25/105 ,  H01L2023/4087 ,  H01L2225/1011 ,  H01L2225/1041

    Abstract: A semiconductor package includes; a lower semiconductor chip mounted on a lower package substrate, an interposer on the lower package substrate and including an opening, connection terminals spaced apart from and at least partially surrounding the lower semiconductor chip and extending between the lower package substrate and the interposer, a first molding member including a first material and covering at least a portion of a top surface of the lower semiconductor chip and at least portions of edge surfaces of the lower semiconductor chip, wherein the first molding member includes a protrusion that extends upward from the opening to cover at least portions of a top surface of the interposer proximate to the opening, and a second molding member including a second material, at least partially surrounding the first molding member, and covering side surfaces of the first molding member and the connection terminals, wherein the first material has thermal conductivity greater than the second material.

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