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    Pseudo main memory system
    1.
    发明授权
    Pseudo main memory system 有权

    公开(公告)号：US10515006B2

    公开(公告)日：2019-12-24

    申请号：US15663619

    申请日：2017-07-28

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Krishna T. Malladi ,  Jongmin Gim ,  Hongzhong Zheng

    IPC: G06F12/02 ,  G06F13/16 ,  G06F12/121

    Abstract: A pseudo main memory system. The system includes a memory adapter circuit for performing memory augmentation using compression, deduplication, and/or error correction. The memory adapter circuit is connected to a memory, and employs the memory augmentation methods to increase the effective storage capacity of the memory. The memory adapter circuit is also connected to a memory bus and implements an NVDIMM-F or modified NVDIMM-F interface for connecting to the memory bus.

    System and method for integrating overprovisioned memory devices
    2.
    发明授权
    System and method for integrating overprovisioned memory devices 有权

    公开(公告)号：US10372606B2

    公开(公告)日：2019-08-06

    申请号：US15282848

    申请日：2016-09-30

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Krishna Malladi ,  Jongmin Gim ,  Hongzhong Zheng

    IPC: G06F12/08 ,  G06F12/0868 ,  G06F12/10

    Abstract: A memory device includes a memory interface to a host computer and a memory overprovisioning logic configured to provide a virtual memory capacity to a host operating system (OS). A kernel driver module of the host OS is configured to manage the virtual memory capacity of the memory device provided by the memory overprovisioning logic of the memory device and provide a fast swap of anonymous pages to a frontswap space and file pages to a cleancache space of the memory device based on the virtual memory capacity of the memory device.

    Tail latency aware foreground garbage collection algorithm
    3.
    发明授权
    Tail latency aware foreground garbage collection algorithm 有权

    公开(公告)号：US10261897B2

    公开(公告)日：2019-04-16

    申请号：US15461467

    申请日：2017-03-16

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Jongmin Gim ,  Hongzhong Zheng

    IPC: G06F12/02

    Abstract: A Solid State Drive (SSD) is disclosed. The SSD may include a host interface logic to receive a write command from a host and flash memory to store data. The SSD may also include an SSD controller, which may include storage for a just-in-time threshold and a tail latency threshold flash translation layer. The flash translation layer may invoke a just-in-time garbage collection strategy when the number of free pages on the SSD is less than the just-in-time threshold, and a tail latency-aware garbage collection strategy when the number of free pages is less than the tail latency threshold. The tail latency-aware garbage collection strategy may pair the write command with a garbage collection command.

    Database offloading engine
    4.
    发明授权
    Database offloading engine 有权

    公开(公告)号：US11334284B2

    公开(公告)日：2022-05-17

    申请号：US16195732

    申请日：2018-11-19

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Andrew Zhenwen Chang ,  Jongmin Gim ,  Hongzhong Zheng

    IPC: G06F3/06 ,  G06F21/62

    Abstract: A database offloading engine. In some embodiments, the database offloading engine includes a vectorized adder including a plurality of read-modify-write circuits, a plurality of sum buffers respectively connected to the read-modify-write circuits, a key address table, and a control circuit. The control circuit may be configured to receive a first key and a corresponding first value; to search the key address table for the first key; and, in response to finding, in the key address table, an address corresponding to the first key, to route the address and the first value to a read-modify-write circuit, of the plurality of read-modify-write circuits, corresponding to the address.

    PSEUDO MAIN MEMORY SYSTEM
    5.
    发明申请
    PSEUDO MAIN MEMORY SYSTEM 有权

    公开(公告)号：US20210271594A1

    公开(公告)日：2021-09-02

    申请号：US17322805

    申请日：2021-05-17

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Krishna T. Malladi ,  Jongmin Gim ,  Hongzhong Zheng

    IPC: G06F12/02 ,  G06F13/16

    Abstract: A pseudo main memory system. The system includes a memory adapter circuit for performing memory augmentation using compression, deduplication, and/or error correction. The memory adapter circuit is connected to a memory, and employs the memory augmentation methods to increase the effective storage capacity of the memory. The memory adapter circuit is also connected to a memory bus and implements an NVDIMM-F or modified NVDIMM-F interface for connecting to the memory bus.

    Opportunity window hints for background operations in SSD
    6.
    发明授权
    Opportunity window hints for background operations in SSD 有权

    公开(公告)号：US10353628B2

    公开(公告)日：2019-07-16

    申请号：US15624430

    申请日：2017-06-15

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Ramdas Kachare ,  Jongmin Gim ,  Yang Seok Ki

    IPC: G06F3/06 ,  G06F12/10 ,  G06F11/34

    Abstract: A method includes: receiving a plurality of host commands from a host to access storage media of a solid-state drive (SSD); monitoring a raw rate for performing the plurality of host commands; calculating an average rate by taking an average of the raw rate over a time unit; comparing the average rate against a threshold; detecting that the average rate falls below the threshold indicating an opening of an opportunity window; providing hints for the opportunity window; and determining whether to perform pending or imminent background operations during the opportunity window.

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