公开(公告)号：US20240354014A1

公开(公告)日：2024-10-24

申请号：US18655510

申请日：2024-05-06

Applicant: Rambus Inc.

Inventor： Thomas Vogelsang ,  Steven C. Woo ,  Michael Raymond Miller

IPC: G06F3/06

CPC classification number: G06F3/0634 ,  G06F3/061 ,  G06F3/0673

Abstract: A memory system includes two or more memory controllers capable of accessing the same dynamic, random-access memory (DRAM), one controller having access to the DRAM or a subset of the DRAM at a time. Different subsets of the DRAM are supported with different refresh-control circuitry, including respective refresh-address counters. Whichever controller has access to a given subset of the DRAM issues refresh requests to the corresponding refresh-address counter. Counters are synchronized before control of a given subset of the DRAM is transferred between controllers to avoid a loss of stored data.

公开(公告)号：US12112051B2

公开(公告)日：2024-10-08

申请号：US18297006

申请日：2023-04-07

Applicant: Hefei Core Storage Electronic Limited

Inventor： Wei Zhong ,  Kai-Di Zhu ,  Zhi Wang ,  Xiaoyang Zhang

IPC: G06F3/06

CPC classification number: G06F3/0634 ,  G06F3/0604 ,  G06F3/0679

Abstract: A valid node management method, a memory storage device and a memory control circuit unit are disclosed. The method includes: establishing a valid node management table corresponding to a first physical management unit; storing valid node management data in the valid node management table, wherein the valid node management data reflects a distribution status of a valid node in the first physical management unit; receiving an operation command from a host system, wherein the operation command is configured to change a data storage status of the first physical management unit; and updating the valid node management data in the valid node management table in response to the operation command.

公开(公告)号：US20240329847A1

公开(公告)日：2024-10-03

申请号：US18129436

申请日：2023-03-31

Applicant: Advanced Micro Devices, Inc.

Inventor： Vignesh Adhinarayanan ,  Michael Ignatowski ,  Hyung-Dong Lee

IPC: G06F3/06

CPC classification number: G06F3/0613 ,  G06F3/0634 ,  G06F3/0659 ,  G06F3/0673

Abstract: A memory sprint controller, responsive to an indicator of an irregular memory access phase, causes a memory controller to enter a sprint mode in which it temporarily adjusts at least one timing parameter of a dynamic random access memory (DRAM) to reduce a time in which a designated number of activate (ACT) commands are allowed to be dispatched to the DRAM.

公开(公告)号：US20240319896A1

公开(公告)日：2024-09-26

申请号：US18598767

申请日：2024-03-07

Applicant: Micron Technology, Inc.

Inventor： Rohit SEHGAL ,  Vishal TANNA ,  Krishna SIDDHAREDDY ,  Eishan MIRAKHUR

IPC: G06F3/06

CPC classification number: G06F3/0634 ,  G06F3/0604 ,  G06F3/0659 ,  G06F3/0673

Abstract: Provided is a system comprising a first interface configured to receive first data from an external computing device, non-volatile memory operatively coupled to the first interface, and a second interface configured to communicate with a host computing device. The system also includes dynamic random-access memory (DRAM) operatively coupled to the second interface, a memory controller operatively coupled to the second interface and the DRAM and configured to control a transfer of information between the DRAM and the host computing device through the second interface, and processing circuitry at least configured to store the first data received through the first interface in the non-volatile memory.

公开(公告)号：US20240319894A1

公开(公告)日：2024-09-26

申请号：US18402721

申请日：2024-01-02

Applicant: SK hynix Inc.

Inventor： Sae Gyeol CHOI ,  Hye Mi KANG

IPC: G06F3/06

CPC classification number: G06F3/0631 ,  G06F3/0604 ,  G06F3/0634 ,  G06F3/0656 ,  G06F3/0679

Abstract: A storage device may dynamically allocate, to a buffer, at least one among M number of buffer units each capable of storing at least one of a plurality of L2P mapping units. When receiving, from an external device, a mapping unit command requesting one or more target L2P mapping units among the plurality of L2P mapping units, the storage device may store the target L2P mapping units in the buffer before transmitting the target L2P mapping units to the external device.

公开(公告)号：US20240302979A1

公开(公告)日：2024-09-12

申请号：US18181610

申请日：2023-03-10

Applicant: Dell Products, L.P.

Inventor： Owen Martin ,  Ramesh Doddaiah

IPC: G06F3/06

CPC classification number: G06F3/0634 ,  G06F3/0604 ,  G06F3/0653 ,  G06F3/067

Abstract: A storage system configuration alternation system implements storage system reconfiguration alternation by determining a first set of storage system optimization policies to be applied during periods where the workload on the storage system is primarily transactional, and determining a second set of storage system optimization policies to be applied during periods where the workload on the storage system is primarily bandwidth intensive. The storage system configuration alternation system monitors the storage system workload to identify whether the storage system workload is primarily transactional or primarily bandwidth intensive. Based on the current monitored determination, the configuration alternation system selectively applies either the first or second set of storage system policies. A primarily bandwidth intensive workload may be determined based on a combination of a high percentage read IO operations of maximum read size, low CPU utilization, and high back-end bandwidth utilization. Policies may include CPU bias, memory segmentation, and LRU bias.

公开(公告)号：US20240302957A1

公开(公告)日：2024-09-12

申请号：US18232060

申请日：2023-08-09

Applicant: WESTERN DIGITAL TECHNOLOGIES, INC.

Inventor： Niles Yang

IPC: G06F3/06

CPC classification number: G06F3/0604 ,  G06F3/0634 ,  G06F3/0679

Abstract: A storage device is communicatively coupled to a host that defines a quality of service level for responses transmitted from the storage device to the host. The storage device includes a memory device to store data. The storage device also includes a controller to perform background operations to manage resources on the memory device while performing foreground operations according to the quality of service level set by the host. The controller generates a free block file including information on free blocks in the memory device and transmits the free block file to the host. The host uses the free block file to determine when the memory device is at or near a critical level of block availability and transmits an indication from to the controller. The controller adjusts the priority of the background operations in response to receipt of the indication to maintain the quality of service level.

公开(公告)号：US12086439B2

公开(公告)日：2024-09-10

申请号：US18343835

申请日：2023-06-29

Applicant: KIOXIA CORPORATION

Inventor： Shunichi Igahara ,  Toshikatsu Hida ,  Riki Suzuki ,  Takehiko Amaki ,  Suguru Nishikawa ,  Yoshihisa Kojima

IPC: G06F3/06 ,  G06F12/02 ,  G06F12/10

CPC classification number: G06F3/0634 ,  G06F3/0604 ,  G06F3/061 ,  G06F3/0619 ,  G06F3/0659 ,  G06F3/0679 ,  G06F12/0253 ,  G06F12/10 ,  G06F2212/1044 ,  G06F2212/657

Abstract: According to one embodiment, a memory system includes a nonvolatile memory and a controller electrically connected to the nonvolatile memory. The controller selects a write mode from a first mode in which data having N bits is written per one memory cell and a second mode in which data having M bits is written per one memory cell. N is equal to or larger than one. M is larger than N. The controller writes data into the nonvolatile memory in the selected write mode. The controller selects either the first mode or the second mode at least based on a total number of logical addresses mapped in a physical address space of the nonvolatile memory.

公开(公告)号：US12086429B2

公开(公告)日：2024-09-10

申请号：US18120733

申请日：2023-03-13

Applicant: Kioxia Corporation

Inventor： Yoko Masuo

IPC: G06F3/06

CPC classification number: G06F3/0625 ,  G06F3/0634 ,  G06F3/064 ,  G06F3/0659 ,  G06F3/0679

Abstract: According to one embodiment, the controller periodically executes a first operation. The controller selects a first mode or a second mode in the first operation. In a case where the first mode is selected, the controller reads pieces of data that are stored in contiguous memory locations, respectively, that are included in a first physical page or a second physical page. The first physical page is included in a first physical block of a first die. The second physical page is included in a second physical block of a second die. In a case where the second mode is selected, the controller reads first data stored in one memory location of the first physical page and second data stored in one memory location of the second physical page.

公开(公告)号：US12086039B2

公开(公告)日：2024-09-10

申请号：US18096812

申请日：2023-01-13

Applicant: Rambus Inc.

Inventor： Frederick A. Ware ,  J. James Tringali ,  Ely Tsern

IPC: G06F11/14 ,  G06F3/06 ,  G11C7/20 ,  G11C14/00

CPC classification number: G06F11/1471 ,  G06F3/0619 ,  G06F3/0634 ,  G06F3/0647 ,  G06F3/0685 ,  G11C7/20 ,  G11C14/0018 ,  G06F2201/805 ,  G06F2201/84

Abstract: The embodiments described herein describe technologies for non-volatile memory persistence in a multi-tiered memory system including two or more memory technologies for volatile memory and non-volatile memory.