公开(公告)号：US20170301381A1

公开(公告)日：2017-10-19

申请号：US15436234

申请日：2017-02-17

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jun SEOMUN ,  Insub Shin ,  Kyungtae Do ,  JungYun Choi

IPC: G11C7/10 ,  G11C7/22

CPC classification number: G11C7/1012 ,  G11C5/143 ,  G11C7/10 ,  G11C7/222

Abstract: Voltage monitors include a predelay cell having an input responsive to a first clock signal. This cell is configured to generate a predelayed clock signal at an output thereof. A serially-connected string of data delay cells is provided, which has an input responsive to the predelayed clock signal. A serially-connected string of clock delay cells is provided, which has an input responsive to a second clock signal that is synchronized to the first clock signal. A plurality latches are provided. The latches have respective data inputs, which are responsive to first periodic signals generated at respective outputs of the serially-connected string of data delay cells, and respective clock/sync terminals, which are responsive to second periodic signals generated at respective outputs of the serially-connected string of clock delay cells. The latches enable loading of a delay code value, which indicates power supply voltage variation.

公开(公告)号：US20210134784A1

公开(公告)日：2021-05-06

申请号：US16992422

申请日：2020-08-13

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Jaehoon KIM ,  Jun SEOMUN ,  Sua LEE ,  Hyungock KIM

IPC: H01L27/02 ,  H01L23/528 ,  H01L29/78 ,  H01L29/06 ,  H01L29/423 ,  H01L29/786 ,  G06F30/392 ,  G06F30/394 ,  G06F30/398

Abstract: A semiconductor device includes standard cells disposed in a first direction parallel to an upper surface of a substrate and a second direction intersecting the first direction, each standard cell including an active region, a gate structure disposed to intersect the active region, source/drain regions on the active region at both sides of the gate structure, and first interconnection lines electrically connected to the active region and the gate structures; filler cells disposed between at least portions of the standard cells, each filler cell including a filler active region and a filler gate structure disposed to intersect the filler active region; and a routing structure disposed on the standard cells and the filler cells and including second interconnection lines electrically connecting the first interconnection lines of different standard cells to each other, wherein the second interconnection lines includes a first line having a first width and a second line having a second width larger than the first width.