公开(公告)号：US20220139901A1

公开(公告)日：2022-05-05

申请号：US17338201

申请日：2021-06-03

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Dayeon CHO ,  Hyungock KIM ,  Sangdo PARK

IPC: H01L27/02 ,  H01L23/528 ,  H01L27/092 ,  H01L29/78 ,  H01L29/06 ,  H01L29/423 ,  H01L29/786 ,  G06F30/392 ,  G06F30/398

Abstract: A semiconductor device includes standard cells in a first direction parallel to an upper surface of a substrate and a second direction intersecting the first direction, and filler cells between ones of the standard cells. Each of the standard cells includes an active region, a gate structure that intersects the active region, source/drain regions on the active region on both sides of the gate structure, and interconnection lines. Each of the filler cells includes a filler active region and a filler gate structure that intersects the filler active region. The standard cells include first to third standard cells in first to third rows sequentially in the second direction, respectively. First interconnection lines are arranged with a first pitch, second interconnection lines are arranged with a second pitch, and third interconnection lines are arranged with a third pitch different from the first and second pitches.

公开(公告)号：US20210134784A1

公开(公告)日：2021-05-06

申请号：US16992422

申请日：2020-08-13

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Jaehoon KIM ,  Jun SEOMUN ,  Sua LEE ,  Hyungock KIM

IPC: H01L27/02 ,  H01L23/528 ,  H01L29/78 ,  H01L29/06 ,  H01L29/423 ,  H01L29/786 ,  G06F30/392 ,  G06F30/394 ,  G06F30/398

Abstract: A semiconductor device includes standard cells disposed in a first direction parallel to an upper surface of a substrate and a second direction intersecting the first direction, each standard cell including an active region, a gate structure disposed to intersect the active region, source/drain regions on the active region at both sides of the gate structure, and first interconnection lines electrically connected to the active region and the gate structures; filler cells disposed between at least portions of the standard cells, each filler cell including a filler active region and a filler gate structure disposed to intersect the filler active region; and a routing structure disposed on the standard cells and the filler cells and including second interconnection lines electrically connecting the first interconnection lines of different standard cells to each other, wherein the second interconnection lines includes a first line having a first width and a second line having a second width larger than the first width.

公开(公告)号：US20210012053A1

公开(公告)日：2021-01-14

申请号：US16795947

申请日：2020-02-20

Applicant: Samsung Electronics Co., Ltd.

Inventor： Kyounghwan LIM ,  Hyungock KIM ,  Heeyeon KIM ,  Dongkwan HAN

IPC: G06F30/392

Abstract: Provided are a system for designing a semiconductor circuit and an operating method of the same. The system includes a working memory loading a clustering application for generating a cluster, based on instances respectively corresponding to cells of the semiconductor circuit, and loading a design tool for placing the cells. The clustering application, when an output terminal of a first instance is connected to a second instance and the number of instances connected to the output terminal of the first instance is one, classifies the first instance and the second instance into a candidate group pair. The clustering application, when all instances connected to an input terminal of the second instance are classified into the candidate group pair with the second instance, generates the cluster including the first instance and the second instance.