公开(公告)号：US11522015B2

公开(公告)日：2022-12-06

申请号：US16789546

申请日：2020-02-13

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Junghoon Bak ,  Woojin Kim ,  Junghwan Moon ,  Seowon Lee ,  Nayoung Ji

IPC: H01L27/24 ,  G11C13/00 ,  H01L27/22

Abstract: A variable resistance memory device includes a first conductive line, a bipolar selection device on the first conductive line and electrically connected to the first conductive line, a second conductive line on the first conductive line and electrically connected to the bipolar selection device, a variable resistance layer on the second conductive line and electrically connected to the second conductive line, and a third conductive line on the variable resistance layer and electrically connected to the variable resistance layer.

公开(公告)号：US11342495B2

公开(公告)日：2022-05-24

申请号：US16789525

申请日：2020-02-13

Applicant: Samsung Electronics Co., Ltd.

Inventor： Junghoon Bak ,  Woojin Kim ,  Junghwan Moon

IPC: H01L43/02 ,  H01L43/12 ,  H01F10/32 ,  H01L43/10

Abstract: Magnetic memory devices may include a substrate, a metal pattern extending in a first direction on the substrate, a magnetic tunnel junction pattern on the metal pattern, and an anti-oxidation layer between the metal pattern and the magnetic tunnel junction pattern. The magnetic tunnel junction pattern may include a first magnetic pattern, a tunnel barrier pattern, and a second magnetic pattern.

公开(公告)号：US11183628B2

公开(公告)日：2021-11-23

申请号：US16829216

申请日：2020-03-25

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Seowon Lee ,  Junghwan Moon ,  Junghoon Bak ,  Woojin Kim ,  Hyeongsun Hong

IPC: G11C11/00 ,  H01L43/02 ,  G11C11/16 ,  H01F10/32 ,  H01L43/10 ,  H01L27/22

Abstract: A magnetic memory device includes a device isolation layer on a substrate and defining an active region, a source region and a drain region apart from each other in the active region of the substrate, a channel portion in the active region of the substrate and between the source region and the drain region, a spin orbit torque (SOT)-inducing layer on the channel portion of the substrate, a magnetic tunnel junction (MTJ) structure on the SOT-inducing layer, the MTJ structure including a free layer on the SOT-inducing layer, a tunnel barrier layer on the free layer, and a pinned layer on the tunnel barrier, a word line on the MTJ structure, a source line electrically connected to the source region, and a bit line electrically connected to the drain region.