公开(公告)号：US20230232619A1

公开(公告)日：2023-07-20

申请号：US17886731

申请日：2022-08-12

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Hosun JUNG ,  Minwu KIM ,  Jungwoo SONG ,  Wonchul LEE

IPC: H01L27/108

CPC classification number: H01L27/10897 ,  H01L27/10814 ,  H01L27/10894

Abstract: A semiconductor memory device includes a substrate including memory cell, peripheral, and intermediate regions; a device isolation pattern; a partitioning pattern; bit lines extending in a first direction to a boundary between the intermediate and peripheral regions; storage node contacts on the memory cell region and filling a lower portion of a space between bit lines; landing pads on the storage node contacts; dummy storage node contacts on the intermediate region and filling a lower portion of a space between bit lines; dummy landing pads on the dummy storage node contacts; and a dam structure on the intermediate region, extending in the first direction, and having a bar shape, wherein the dummy landing pads are spaced apart from an edge of the dam structure in a second direction, and the dummy storage node contacts are in contact with the partitioning pattern.

公开(公告)号：US20230232612A1

公开(公告)日：2023-07-20

申请号：US18050179

申请日：2022-10-27

Applicant: Samsung Electronics Co., Ltd.

Inventor： Chanwoo Shin ,  Hyuckjin KANG ,  Donghwan LEE ,  Jeonil LEE ,  Minwu KIM ,  Jungwoo SONG

IPC: H01L29/94

CPC classification number: H01L27/10814 ,  H01L27/10885 ,  H01L27/10855

Abstract: A semiconductor device includes a bit line structure on a substrate, a lower contact plug on a portion of the substrate adjacent to the bit line structure, an upper contact plug including a first metal pattern on the lower contact plug and a second metal pattern contacting an upper surface and an upper sidewall of the first metal pattern, and a capacitor on the upper contact plug. The upper surface of the first metal pattern is above an upper surface of the bit line structure with respect to an upper surface of the substrate.

公开(公告)号：US20230113319A1

公开(公告)日：2023-04-13

申请号：US17961635

申请日：2022-10-07

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Bonhong GU ,  Minwoo KIM ,  Jinyong KIM ,  Hyodong BAN ,  Jungwoo SONG ,  Daegwon HA

IPC: H01L27/108

Abstract: A semiconductor device includes conductive patterns, an insulating pattern between the conductive patterns, an insulating etch stop layer on the conductive patterns and the insulating pattern, a capacitor including first electrodes in contact with the first conductive patterns, a second capacitor electrode, and a dielectric between the first and second capacitor electrodes, an insulating structure covering the capacitor and the insulating etch stop layer, and a peripheral contact plug through the insulating structure and the insulating etch stop layer and including first through fifth plug regions stacked on top of each other, at least a portion of a side surface of the fourth plug region having an inclination angle different from inclinations angles of the third and fifth plug regions, and a vertical thickness of the fifth plug region being at least twice as great as a sum of vertical thicknesses of the first to fourth plug regions.

公开(公告)号：US20240251547A1

公开(公告)日：2024-07-25

申请号：US18406265

申请日：2024-01-08

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Byeongjun BAE ,  Jungwoo SONG

IPC: H10B12/00

CPC classification number: H10B12/34 ,  H10B12/053 ,  H10B12/315 ,  H10B12/482 ,  H10B12/488

Abstract: A semiconductor device includes: an active area formed on a substrate; bit lines extending in a first direction and formed inside the substrate by passing through the active area, wherein the bit lines are formed at first intervals in a second direction that is substantially perpendicular to the first direction; word lines formed inside the substrate by passing through the active area, and extending below the bit lines in the second direction, wherein the word lines are formed at second intervals in the first direction; a contact structure formed on the active area and adjacent to the bit lines, wherein the contact structure includes a metal layer and an adhesive layer; and a capacitor structure formed on the contact structure, wherein the active area is inclined in a third direction having a certain slope with respect to the first direction.

公开(公告)号：US20210335790A1

公开(公告)日：2021-10-28

申请号：US17371452

申请日：2021-07-09

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Jungwoo SONG ,  Kwangmin KIM ,  Jun Ho LEE ,  Hyuckjin KANG ,  Yong Kwan KIM ,  Sangyeon HAN ,  Seguen PARK

IPC: H01L27/108 ,  H01L29/06 ,  H01L23/532 ,  H01L27/24 ,  H01L27/22

Abstract: Provided are a semiconductor memory device and a method of fabricating the same. The semiconductor memory device may include: a first impurity doped region and a second impurity doped region spaced apart from each other in a semiconductor substrate, a bit line electrically connected to the first impurity doped region and crossing over the semiconductor substrate, a storage node contact electrically connected to the second impurity doped region, a first spacer and a second spacer disposed between the bit line and the storage node contact, and an air gap region disposed between the first spacer and the second spacer. The first spacer may cover a sidewall of the bit line, and the second spacer may be adjacent to the storage node contact. A top end of the first spacer may have a height higher than a height of a top end of the second spacer.