公开(公告)号：US20150006762A1

公开(公告)日：2015-01-01

申请号：US14316655

申请日：2014-06-26

Applicant: Samsung Electronics Co., Ltd.

Inventor： Keongho Lee ,  Seungbeom Lee ,  Joongbaik Kim ,  Seungwook Lee ,  Chunmok Chung

IPC: G06F3/06

CPC classification number: G06F13/1673

Abstract: A method for controlling a memory operation includes determining a number of commands for each memory address based on information of requests stored in an interface buffer and a scheduler buffer, determining a control state of the memory operation according to a command type with a largest number of commands, and determining types of a request transmitted to the scheduler buffer from the interface buffer and a request output from the scheduler buffer according to a control state of the memory operation. Other embodiments including an apparatus for controlling a memory are also disclosed.

Abstract translation: 一种用于控制存储器操作的方法包括基于存储在接口缓冲器和调度器缓冲器中的请求的信息来确定每个存储器地址的命令数量，根据具有最大数量的存储器操作的命令类型确定存储器操作的控制状态 命令，以及根据存储器操作的控制状态确定从接口缓冲器发送到调度器缓冲器的请求的类型和从调度器缓冲器输出的请求。 还公开了包括用于控制存储器的装置的其它实施例。

公开(公告)号：US10275371B2

公开(公告)日：2019-04-30

申请号：US14316655

申请日：2014-06-26

Applicant: Samsung Electronics Co., Ltd.

Inventor： Keongho Lee ,  Seungbeom Lee ,  Joongbaik Kim ,  Seungwook Lee ,  Chunmok Chung

IPC: G06F3/06 ,  G06F13/16

Abstract: A method for controlling a memory operation includes determining a number of commands for each memory address based on information of requests stored in an interface buffer and a scheduler buffer, determining a control state of the memory operation according to a command type with a largest number of commands, and determining types of a request transmitted to the scheduler buffer from the interface buffer and a request output from the scheduler buffer according to a control state of the memory operation. Other embodiments including an apparatus for controlling a memory are also disclosed.

公开(公告)号：US11809339B2

公开(公告)日：2023-11-07

申请号：US17191255

申请日：2021-03-03

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Keongho Lee ,  Youngseh Kim ,  Wonjin Kim ,  Seungbeom Lee

IPC: G06F13/16 ,  G06F16/23

CPC classification number: G06F13/1668 ,  G06F16/2379

Abstract: A data bus includes: a transaction selection circuit configured to receive vector data including a plurality of transactions from outside of the data bus, select at least one transaction from the plurality of transactions in which no traffic conflict occurs based on whether there is a traffic conflict among the plurality of transactions, and output the selected at least one transaction; and a memory data path including at least one register and configured to output the selected at least one transaction provided by the transaction selection circuit via the at least one register to the outside of the data bus.

公开(公告)号：US10474574B2

公开(公告)日：2019-11-12

申请号：US15781316

申请日：2016-12-02

Applicant: Samsung Electronics Co., Ltd.

Inventor： Changhun Yu ,  Wonjin Kim ,  Hyunsik Kim ,  Sunho Moon ,  Minwook Ahn ,  Rakie Kim ,  Kyoungsoo Cho ,  Nikunj Saunshi ,  Parichay Kapoor ,  Pankaj Agarwal ,  Won-Sub Kim ,  Jin-Hyo Kim ,  Hyunghoon Kim ,  Jisu Oh ,  Keongho Lee ,  Seung-Beom Lee ,  Jinseok Lee ,  Dong-Gi Jang ,  Subin Jo ,  Apoorv Kansal

IPC: G06F12/00 ,  G06F12/06 ,  G06F12/02 ,  G06F12/0882 ,  G06F9/50 ,  G06F12/0817 ,  G06F12/1009

Abstract: The present disclosure relates to system resource management in a variety of situations. The present disclosure provides a method and an apparatus for reducing memory requirements and improving processing speed when an electronic device performs padding for a particular arithmetic operation on data. To achieve the above objective, a method for operating an electronic device according to the present disclosure comprises the steps of: reading a first portion of data from a first memory; determining a first padding address based on the address of a byte belonging to a boundary region of the data among a plurality of bytes included in the first portion; writing values of the plurality of bytes and a value corresponding to the first padding address to a second memory; and reading a second portion of the data from the first memory.