公开(公告)号：US09632978B2

公开(公告)日：2017-04-25

申请号：US13827280

申请日：2013-03-14

Applicant: Samsung Electronics Co., Ltd.

Inventor： Hae-Woo Park ,  Won-Sub Kim

IPC: G06F9/30 ,  G06F15/80 ,  G06F9/45 ,  G06F15/78 ,  G06F9/38

CPC classification number: G06F15/80 ,  G06F8/4452 ,  G06F9/3012 ,  G06F9/3891 ,  G06F15/7867 ,  G06F15/8023

Abstract: A reconfigurable processor based on mini-cores (MCs) includes a plurality of MCs, each MC of the MCs including a group of function units (FUs), the group of FUs having a capability of executing a loop iteration independently. The MCs include a first MC configured to execute a first loop iteration, and a second MC configured to execute a second loop iteration.

公开(公告)号：US10474574B2

公开(公告)日：2019-11-12

申请号：US15781316

申请日：2016-12-02

Applicant: Samsung Electronics Co., Ltd.

Inventor： Changhun Yu ,  Wonjin Kim ,  Hyunsik Kim ,  Sunho Moon ,  Minwook Ahn ,  Rakie Kim ,  Kyoungsoo Cho ,  Nikunj Saunshi ,  Parichay Kapoor ,  Pankaj Agarwal ,  Won-Sub Kim ,  Jin-Hyo Kim ,  Hyunghoon Kim ,  Jisu Oh ,  Keongho Lee ,  Seung-Beom Lee ,  Jinseok Lee ,  Dong-Gi Jang ,  Subin Jo ,  Apoorv Kansal

IPC: G06F12/00 ,  G06F12/06 ,  G06F12/02 ,  G06F12/0882 ,  G06F9/50 ,  G06F12/0817 ,  G06F12/1009

Abstract: The present disclosure relates to system resource management in a variety of situations. The present disclosure provides a method and an apparatus for reducing memory requirements and improving processing speed when an electronic device performs padding for a particular arithmetic operation on data. To achieve the above objective, a method for operating an electronic device according to the present disclosure comprises the steps of: reading a first portion of data from a first memory; determining a first padding address based on the address of a byte belonging to a boundary region of the data among a plurality of bytes included in the first portion; writing values of the plurality of bytes and a value corresponding to the first padding address to a second memory; and reading a second portion of the data from the first memory.

公开(公告)号：US20130246735A1

公开(公告)日：2013-09-19

申请号：US13827280

申请日：2013-03-14

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Hae-Woo Park ,  Won-Sub Kim

IPC: G06F15/80

CPC classification number: G06F15/80 ,  G06F8/4452 ,  G06F9/3012 ,  G06F9/3891 ,  G06F15/7867 ,  G06F15/8023

Abstract: A reconfigurable processor based on mini-cores (MCs) includes a plurality of MCs, each MC of the MCs including a group of function units (FUs), the group of FUs having a capability of executing a loop iteration independently. The MCs include a first MC configured to execute a first loop iteration, and a second MC configured to execute a second loop iteration.

Abstract translation: 基于微型核心（MC）的可重构处理器包括多个MC，MC的每个MC包括一组功能单元（FU），该组具有独立地执行循环迭代的能力。 MC包括被配置为执行第一循环迭代的第一MC，以及被配置为执行第二循环迭代的第二MC。

公开(公告)号：US10223269B2

公开(公告)日：2019-03-05

申请号：US15121999

申请日：2015-02-26

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Won-Sub Kim ,  Tai-song Jin ,  Do-hyung Kim ,  Seung-won Lee

IPC: G06F12/08 ,  G06F12/0844 ,  G06F13/372 ,  G06F13/376 ,  G06F13/16 ,  G06F9/38 ,  G06F9/52 ,  G06F9/48

Abstract: A method of preventing a bank conflict in a memory includes determining processing timing of each of threads of function units to access a first memory bank in which occurrence of a bank conflict is expected, setting a variable latency of each of the threads for sequential access of the threads according to the determined processing timing, sequentially storing the threads in a data memory queue according to the determined processing timing, and performing an operation by allowing the threads stored in the data memory queue to sequentially access the first memory bank whenever the variable latency of each of the threads passes.

公开(公告)号：US09411582B2

公开(公告)日：2016-08-09

申请号：US13832291

申请日：2013-03-15

Applicant: Samsung Electronics Co., Ltd. ,  Seoul National University R&DB Foundation

Inventor： Seong-Hun Jeong ,  Bernhard Egger ,  Won-Sub Kim

IPC: G06F9/30 ,  G06F9/38 ,  G06F15/78 ,  G06F9/45

CPC classification number: G06F9/30007 ,  G06F8/443 ,  G06F9/30072 ,  G06F9/30105 ,  G06F9/3859 ,  G06F15/7867

Abstract: An apparatus for processing an invalid operation in a prologue and/or an epilogue of a loop includes a register file including a first region for storing a data validity value indicating whether data is valid or invalid, and a second region for storing the data; and a functional unit configured to determine whether an operation is valid or invalid based on a value of a first region of each of one or more input sources received from the register file, and output a destination including a value based on the value of the first region of each of the input sources.

Abstract translation: 一种用于在循环的序言和/或循环的结尾处理无效操作的装置包括：寄存器文件，包括用于存储指示数据是有效还是无效的数据有效值的第一区域和用于存储数据的第二区域; 以及功能单元，被配置为基于从所述寄存器文件接收到的一个或多个输入源中的每一个的第一区域的值来确定操作是有效还是无效，并且基于所述第一 每个输入源的区域。

公开(公告)号：US09311270B2

公开(公告)日：2016-04-12

申请号：US14197591

申请日：2014-03-05

Applicant: Samsung Electronics Co., Ltd.

Inventor： Won-Sub Kim ,  Yoonseo Choi ,  Hae-Woo Park

IPC: G06F9/46 ,  G06F15/78 ,  G06F9/48

CPC classification number: G06F15/7885 ,  G06F9/4881

Abstract: A scheduler and scheduling method perform scheduling for a reconfigurable architecture. The scheduling, performed by the scheduler, includes path information extracting including extracting direct path information and indirect path information between functional units in a reconfigurable array complying with predefined architecture requirements, based on architecture information of the reconfigurable array, command selecting including selecting a command from a data flow graph (DFG) showing commands to be executed by the reconfigurable array, and scheduling including scheduling the selected command based on the extracted direct path information and indirect path information.

Abstract translation: 调度器和调度方法对可重构架构执行调度。 由调度器执行的调度包括路径信息提取，包括基于可重配置阵列的体系结构信息，在可重配置阵列的可重构阵列中的功能单元之间提取直接路径信息和间接路径信息，命令选择包括从 显示由可重配置阵列执行的命令的数据流图（DFG），以及包括基于所提取的直接路径信息和间接路径信息来调度所选择的命令的调度。