公开(公告)号：US20190140665A1

公开(公告)日：2019-05-09

申请号：US16013053

申请日：2018-06-20

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Dong-Min SHIN ,  Min Uk KIM ,  Ki Jun LEE ,  Jun Jin KONG ,  Hong Rak SON

IPC: H03M13/29 ,  H03M13/13

Abstract: A polar code encoding and decoding method includes generating a first and second sub-codewords. The sub-codewords correspond to pre-codewords, and the pre-codewords have a shared data aspect. The sub-codewords provide useful error-recovery for data stored in a memory. When data is read from the memory, decoding takes place. The data read operation may include hard decision decoding, soft decision decoding, or hard decision decoding followed by soft decision decoding. In the method, the shared data aspect is used to decode a first sub-codeword for which decoding was not initially successful. An apparatus is also provided.

公开(公告)号：US20210004289A1

公开(公告)日：2021-01-07

申请号：US17029912

申请日：2020-09-23

Applicant: Samsung Electronics Co., Ltd.

Inventor： Myung Kyu LEE ,  Jun Jin KONG ,  Ki Jun LEE ,  Sung Hye CHO ,  Dae Hyun KIM ,  Yong Gyu CHU

IPC: G06F11/10 ,  H03M13/29 ,  G11C29/52

Abstract: Disclosed are a semiconductor memory device, a controller, a memory system, and an operation method thereof. The semiconductor memory device includes a memory cell array including a plurality of memory cells, and an error correcting code (ECC) decoder configured to receive first data and a parity output from selected memory cells of the memory cell array. The ECC decoder generates a syndrome based on the first data and the parity, generates a decoding status flag (DSF) indicating a type of an error of the first data by the syndrome, and outputs the second data and the DSF to an external device outside of the semiconductor memory device when a read operation of the semiconductor memory device is performed.

公开(公告)号：US20200133768A1

公开(公告)日：2020-04-30

申请号：US16372047

申请日：2019-04-01

Applicant: Samsung Electronics Co., Ltd.

Inventor： Myung Kyu LEE ,  Jun Jin KONG ,  Ki Jun LEE ,  Sung Hye CHO ,  Dae Hyun KIM ,  Yong Gyu CHU

IPC: G06F11/10 ,  G11C29/52 ,  H03M13/29

Abstract: Disclosed are a semiconductor memory device, a controller, and a memory system. The semiconductor memory device includes a memory cell array including a plurality of memory cells, and an error correcting code (ECC) decoder configured to receive first data and a parity output from selected memory cells of the memory cell array. The ECC decoder generates a syndrome based on the first data and the parity, generates a decoding status flag (DSF) indicating a type of an error of the first data by the syndrome, and outputs the second data and the DSF to an external device outside of the semiconductor memory device when a read operation of the semiconductor memory device is performed.

公开(公告)号：US20230142474A1

公开(公告)日：2023-05-11

申请号：US18093560

申请日：2023-01-05

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Sung-Rae KIM ,  Myung Kyu LEE ,  Ki Jun LEE ,  Jun Jin KONG ,  Yeong Geol SONG ,  Jin-Hoon JANG

IPC: G11C29/42 ,  G11C29/44 ,  G11C29/00 ,  G11C29/18 ,  G11C29/14

CPC classification number: G11C29/42 ,  G11C29/4401 ,  G11C29/783 ,  G11C29/18 ,  G11C29/14

Abstract: A memory device includes a memory cell array including memory cells arranged in a plurality of rows; an ECC engine configured to detect an error in first data that is read from the memory cell array in response to a read command and a read address, to output a first error occurrence signal, and to correct the error in the first data; a row fail detector configured to output a fail row address, which indicates a fail row among the plurality of rows; and a flag generator configured to receive the read address, the first error occurrence signal, and the fail row address, and to generate a decoding state flag, which indicates whether an error is detected and whether an error is corrected, and a fail row flag, which indicates that a read row address included in the read address is the fail row address.

公开(公告)号：US20220180958A1

公开(公告)日：2022-06-09

申请号：US17392382

申请日：2021-08-03

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Sung-Rae KIM ,  Myung Kyu LEE ,  Ki Jun LEE ,  Jun Jin KONG ,  Yeong Geol SONG ,  Jin-Hoon JANG

IPC: G11C29/42 ,  G11C29/44 ,  G11C29/14 ,  G11C29/18 ,  G11C29/00

Abstract: A memory device includes a memory cell array including memory cells arranged in a plurality of rows; an ECC engine configured to detect an error in first data that is read from the memory cell array in response to a read command and a read address, to output a first error occurrence signal, and to correct the error in the first data; a row fail detector configured to output a fail row address, which indicates a fail row among the plurality of rows; and a flag generator configured to receive the read address, the first error occurrence signal, and the fail row address, and to generate a decoding state flag, which indicates whether an error is detected and whether an error is corrected, and a fail row flag, which indicates that a read row address included in the read address is the fail row address.