公开(公告)号：US20140227841A1

公开(公告)日：2014-08-14

申请号：US14258436

申请日：2014-04-22

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jaegoo LEE ,  Kil-Su JEONG ,  Hansoo KIM ,  Youngwoo PARK

IPC: H01L27/115

CPC classification number: H01L23/52 ,  H01L27/1157 ,  H01L27/11578 ,  H01L27/11582 ,  H01L2924/0002 ,  H01L2924/00

Abstract: Example embodiments relate to a three-dimensional semiconductor memory device including an electrode structure on a substrate, the electrode structure including at least one conductive pattern on a lower electrode, and a semiconductor pattern extending through the electrode structure to the substrate. A vertical insulating layer may be between the semiconductor pattern and the electrode structure, and a lower insulating layer may be between the lower electrode and the substrate. The lower insulating layer may be between a bottom surface of the vertical insulating layer and a top surface of the substrate. Example embodiments related to methods for fabricating the foregoing three-dimensional semiconductor memory device.

Abstract translation: 示例实施例涉及一种三维半导体存储器件，其包括在衬底上的电极结构，该电极结构包括在下电极上的至少一个导电图案，以及半导体图案，其延伸穿过该电极结构到该衬底。 垂直绝缘层可以在半导体图案和电极结构之间，下绝缘层可以位于下电极和衬底之间。 下绝缘层可以在垂直绝缘层的底表面和基板的顶表面之间。 与制造上述三维半导体存储器件的方法相关的示例实施例。

公开(公告)号：US20150064867A1

公开(公告)日：2015-03-05

申请号：US14536328

申请日：2014-11-07

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Kil-Su JEONG

IPC: H01L27/115

CPC classification number: H01L27/11582 ,  H01L27/0688 ,  H01L27/101 ,  H01L27/11556 ,  H01L29/7926

Abstract: A three-dimensional semiconductor device and a method of fabricating the same, the device including a lower insulating layer on a top surface of a substrate; an electrode structure sequentially stacked on the lower insulating layer, the electrode structure including conductive patterns; a semiconductor pattern penetrating the electrode structure and the lower insulating layer and being connected to the substrate; and a vertical insulating layer interposed between the semiconductor pattern and the electrode structure, the vertical insulating layer crossing the conductive patterns in a vertical direction and being in contact with a top surface of the lower insulating layer.

Abstract translation: 一种三维半导体器件及其制造方法，所述器件在衬底的顶表面上包括下绝缘层; 依次堆叠在下绝缘层上的电极结构，所述电极结构包括导电图案; 穿过电极结构和下绝缘层并连接到衬底的半导体图案; 以及插入在所述半导体图案和所述电极结构之间的垂直绝缘层，所述垂直绝缘层在垂直方向上与所述导电图案交叉并且与所述下绝缘层的顶表面接触。