公开(公告)号：US20140065810A1

公开(公告)日：2014-03-06

申请号：US14074817

申请日：2013-11-08

申请人： SAMSUNG ELECTRONICS CO., LTD.

发明人： Byoungkeun SON ,  Changhyun LEE ,  Jaegoo LEE ,  Kwang Soo SEOL ,  Byungkwan YOU

IPC分类号： H01L29/66

CPC分类号： H01L29/66833 ,  H01L27/11582 ,  H01L29/7926

摘要： A nonvolatile memory device and a method of forming the same, the device including a semiconductor substrate; a plurality of gate patterns stacked on the semiconductor substrate; inter-gate dielectric patterns between the gate patterns; active pillars sequentially penetrating the gate patterns and the inter-gate dielectric patterns to contact the semiconductor substrate; and a gate insulating layer between the active pillars and the gate patterns, wherein corners of the gate patterns adjacent to the active pillars are rounded.

摘要翻译： 非易失性存储器件及其形成方法，所述器件包括半导体衬底; 堆叠在所述半导体衬底上的多个栅极图案; 栅极图案之间的栅极间电介质图案; 依次穿过栅极图案和栅极间电介质图案以接触半导体衬底的有源支柱; 以及在活性柱和栅极图案之间的栅极绝缘层，其中与活性柱相邻的栅极图案的角部是圆形的。

公开(公告)号：US20140367764A1

公开(公告)日：2014-12-18

申请号：US14472952

申请日：2014-08-29

申请人： SAMSUNG ELECTRONICS CO., LTD.

发明人： Jaegoo LEE ,  Youngwoo PARK ,  Jungdal CHOI

IPC分类号： H01L27/115 ,  H01L29/423 ,  H01L29/78

CPC分类号： H01L27/11578 ,  H01L27/11582 ,  H01L29/4234 ,  H01L29/7827 ,  H01L29/7926

摘要： A method of fabricating a semiconductor memory device includes forming a mold stack on a substrate and the mold stack including first sacrificial layers and second sacrificial layers alternately stacked on the substrate. The method also includes forming a plurality of vertical channels that penetrate the mold stack and that contact the substrate, patterning the mold stack to form word line cuts between the vertical channels, the word line cuts exposing the substrate, removing one of the first and second sacrificial layers to form recessed regions in the mold stack, forming a data storage layer, at least a portion of the data storage layer being formed between the vertical channels and the gates, forming gates in the recessed regions, forming air gaps between the gates by removing the other of the first and second sacrificial layers, and forming an insulation layer pattern in the word line cuts.

摘要翻译： 一种制造半导体存储器件的方法包括在衬底上形成模具堆叠，并且模具叠层包括交替层叠在衬底上的第一牺牲层和第二牺牲层。 该方法还包括形成多个垂直通道，其穿过模具叠层并与衬底接触，图案化模具叠层以形成垂直通道之间的字线切口，字线切割暴露衬底，去除第一和第二 牺牲层，以在模具堆叠中形成凹陷区域，形成数据存储层，数据存储层的至少一部分形成在垂直沟道和栅极之间，在凹陷区域中形成栅极，在栅极之间形成气隙，通过 去除第一和第二牺牲层中的另一个，并且在字线切割中形成绝缘层图案。

公开(公告)号：US20210183771A1

公开(公告)日：2021-06-17

申请号：US16933133

申请日：2020-07-20

申请人： SAMSUNG ELECTRONICS CO., LTD.

发明人： Jaegoo LEE

IPC分类号： H01L23/535 ,  H01L27/11519 ,  H01L27/11556 ,  H01L27/11565 ,  H01L27/11582 ,  H01L23/522 ,  H01L23/528 ,  H01L21/768

摘要： A semiconductor device a substrate; conductive patterns on the substrate, the conductive patterns being spaced apart from each other in a vertical direction perpendicular to a surface of the substrate, and an edge of the conductive patterns including a step portion such that an end of one conductive pattern is not overlapped in the vertical direction with conductive patterns positioned thereover; insulation patterns between the conductive patterns; sidewall insulation patterns on the sidewalls of the conductive patterns to cover sidewalls of the conductive patterns; upper pad patterns on upper surfaces of the step portion of the conductive patterns and upper surfaces of a portion of the sidewall insulation patterns; an insulating interlayer covering the conductive patterns, the insulation patterns, the sidewall insulation patterns, and the upper pad patterns; and contact plugs passing through the insulating interlayer, the contact plugs contacting the upper pad patterns, respectively.

公开(公告)号：US20140227841A1

公开(公告)日：2014-08-14

申请号：US14258436

申请日：2014-04-22

申请人： Samsung Electronics Co., Ltd.

发明人： Jaegoo LEE ,  Kil-Su JEONG ,  Hansoo KIM ,  Youngwoo PARK

IPC分类号： H01L27/115

CPC分类号： H01L23/52 ,  H01L27/1157 ,  H01L27/11578 ,  H01L27/11582 ,  H01L2924/0002 ,  H01L2924/00

摘要： Example embodiments relate to a three-dimensional semiconductor memory device including an electrode structure on a substrate, the electrode structure including at least one conductive pattern on a lower electrode, and a semiconductor pattern extending through the electrode structure to the substrate. A vertical insulating layer may be between the semiconductor pattern and the electrode structure, and a lower insulating layer may be between the lower electrode and the substrate. The lower insulating layer may be between a bottom surface of the vertical insulating layer and a top surface of the substrate. Example embodiments related to methods for fabricating the foregoing three-dimensional semiconductor memory device.

摘要翻译： 示例实施例涉及一种三维半导体存储器件，其包括在衬底上的电极结构，该电极结构包括在下电极上的至少一个导电图案，以及半导体图案，其延伸穿过该电极结构到该衬底。 垂直绝缘层可以在半导体图案和电极结构之间，下绝缘层可以位于下电极和衬底之间。 下绝缘层可以在垂直绝缘层的底表面和基板的顶表面之间。 与制造上述三维半导体存储器件的方法相关的示例实施例。

公开(公告)号：US20210233928A1

公开(公告)日：2021-07-29

申请号：US16885597

申请日：2020-05-28

申请人： SAMSUNG ELECTRONICS CO., LTD.

发明人： Jaegoo LEE

IPC分类号： H01L27/11582 ,  H01L27/11565 ,  H01L27/11573 ,  H01L27/11519 ,  H01L27/11526 ,  H01L27/11556 ,  H01L23/522 ,  G11C8/14 ,  G11C7/18

摘要： A 3D memory device and a method of manufacturing the same, the device including a substrate including a cell and an extension region; a cell stack including insulation layers and word lines alternately stacked on the substrate; channel structures vertically passing through the cell stack; a word line separation layer vertically passing through the cell stack and extending lengthwise in a first direction; a contact plug vertically connected to the word lines on the extension region; and a bit line extending lengthwise in a second direction on the channel structures, wherein each of the word lines includes an inner pattern including polysilicon; and an outer pattern including metal, the outer pattern surrounds an outer surface of the inner pattern, the channel structures vertically pass through the inner pattern, and the contact plug is on the outer pattern.

公开(公告)号：US20140231899A1

公开(公告)日：2014-08-21

申请号：US14265959

申请日：2014-04-30

申请人： Samsung Electronics Co., Ltd.

发明人： Jaegoo LEE ,  Byungkwan YOU ,  Youngwoo PARK ,  Kwang Soo SEOL

IPC分类号： H01L27/115

CPC分类号： H01L21/3205 ,  H01L27/11578 ,  H01L27/11582

摘要： Methods of manufacturing three-dimensional semiconductor devices that may include forming a first spacer on a sidewall inside a first opening formed in a first stack structure, forming a sacrificial filling pattern on the spacer to fill the first opening, forming a second stack structure including a second opening exposing the sacrificial filling pattern on the first stack structure, forming a second spacer on a sidewall inside the second opening, removing the sacrificial filling pattern and removing the first spacer and the second spacer.

摘要翻译： 制造三维半导体器件的方法，其可以包括在形成在第一堆叠结构中的第一开口内的侧壁上形成第一间隔物，在间隔物上形成牺牲填充图案以填充第一开口，形成第二堆叠结构， 在所述第一堆叠结构上暴露所述牺牲填充图案的第二开口，在所述第二开口内的侧壁上形成第二间隔件，去除所述牺牲填充图案并移除所述第一间隔件和所述第二间隔件。