公开(公告)号：US20230185739A1

公开(公告)日：2023-06-15

申请号：US17586767

申请日：2022-01-27

Applicant: Samsung Electronics Co., Ltd.

Inventor： Marie Mai NGUYEN ,  Rekha PITCHUMANI ,  Zongwang LI ,  Yang Seok KI ,  Krishna Teja MALLADI

IPC: G06F13/16

CPC classification number: G06F13/1668

Abstract: An accelerator is disclosed. A circuit may process a data to produce a processed data. A first tier storage may include a first capacity and a first latency. A second tier storage may include a second capacity and a second latency. The second capacity may be larger than the first capacity, and the second latency may be slower than the first latency. A bus may be used to transfer at least one of the data or the processed data between the first tier storage and the second tier storage.

公开(公告)号：US20230185740A1

公开(公告)日：2023-06-15

申请号：US17586770

申请日：2022-01-27

Applicant: Samsung Electronics Co., Ltd.

Inventor： Marie Mai NGUYEN ,  Rekha PITCHUMANI ,  Yang Seok KI ,  Krishna Teja MALLADI

IPC: G06F13/16 ,  G06F13/42 ,  G06F9/30

CPC classification number: G06F13/1668 ,  G06F13/1663 ,  G06F13/4221 ,  G06F9/30043 ,  G06F9/30047

Abstract: An accelerator is disclosed. A tier storage may store data. A circuit may process the data to produce a processed data. The accelerator may load the data from a device using a cache-coherent interconnect protocol.

公开(公告)号：US20250036590A1

公开(公告)日：2025-01-30

申请号：US18919270

申请日：2024-10-17

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Krishna Teja MALLADI ,  Andrew CHANG ,  Byung Hee CHOI ,  Ehsan M. NAJAFABADI

IPC: G06F13/40 ,  G06F3/06 ,  G06F9/4401 ,  G06F12/0802 ,  G06F12/0808 ,  G06F12/1045 ,  G06F13/16 ,  G06F13/28 ,  G06F13/42 ,  G06F15/173 ,  H04L49/351 ,  H04L49/45

Abstract: A system and method for managing memory resources. In some embodiments, the system includes a stored-program processing circuit, a network interface circuit, a cache-coherent switch, and a first memory module. In some embodiments, the first memory module is connected to the cache-coherent switch, the cache-coherent switch is connected to the network interface circuit, and the stored-program processing circuit is connected to the cache-coherent switch.

公开(公告)号：US20210311897A1

公开(公告)日：2021-10-07

申请号：US17026071

申请日：2020-09-18

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Krishna Teja MALLADI ,  Andrew CHANG ,  Ehsan M. NAJAFABADI

IPC: G06F13/40 ,  G06F12/1045 ,  G06F13/16 ,  G06F15/173 ,  G06F13/42 ,  G06F12/0808

Abstract: A system and method for managing memory resources. In some embodiments the system includes a first server, including a stored-program processing circuit, a first network interface circuit, and a first memory module. The first memory module may include a first memory die, and a controller. The controller may be connected to the first memory die through a memory interface, to the stored-program processing circuit through a cache-coherent interface, and to the first network interface circuit.