公开(公告)号：US20140065810A1

公开(公告)日：2014-03-06

申请号：US14074817

申请日：2013-11-08

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Byoungkeun SON ,  Changhyun LEE ,  Jaegoo LEE ,  Kwang Soo SEOL ,  Byungkwan YOU

IPC: H01L29/66

CPC classification number: H01L29/66833 ,  H01L27/11582 ,  H01L29/7926

Abstract: A nonvolatile memory device and a method of forming the same, the device including a semiconductor substrate; a plurality of gate patterns stacked on the semiconductor substrate; inter-gate dielectric patterns between the gate patterns; active pillars sequentially penetrating the gate patterns and the inter-gate dielectric patterns to contact the semiconductor substrate; and a gate insulating layer between the active pillars and the gate patterns, wherein corners of the gate patterns adjacent to the active pillars are rounded.

Abstract translation: 非易失性存储器件及其形成方法，所述器件包括半导体衬底; 堆叠在所述半导体衬底上的多个栅极图案; 栅极图案之间的栅极间电介质图案; 依次穿过栅极图案和栅极间电介质图案以接触半导体衬底的有源支柱; 以及在活性柱和栅极图案之间的栅极绝缘层，其中与活性柱相邻的栅极图案的角部是圆形的。

公开(公告)号：US20150357339A1

公开(公告)日：2015-12-10

申请号：US14826814

申请日：2015-08-14

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Sunil SHIM ,  Jang-Gn YUN ,  Jeonghyuk CHOI ,  Kwang Soo SEOL ,  Jaehoon JANG ,  Jungdal CHOI

IPC: H01L27/115 ,  H01L23/535

CPC classification number: G11C16/0466 ,  G11C16/0483 ,  H01L23/535 ,  H01L27/11524 ,  H01L27/11556 ,  H01L27/1157 ,  H01L27/11582 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A semiconductor memory device is provided including first and second cell strings formed on a substrate, the first and second cell strings jointly connected to a bit line, wherein each of the first and second cell strings includes a ground selection unit, a memory cell, and first and second string selection units sequentially formed on the substrate to be connected to each other, wherein the ground selection unit is connected to a ground selection line, the memory cell is connected to a word line, the first string selection unit is connected to a first string selection line, and the second string selection unit is connected to a second string selection line, and wherein the second string selection unit of the first cell string has a channel dopant region.

Abstract translation: 提供一种半导体存储器件，包括形成在衬底上的第一和第二单元串，第一和第二单元串共同连接到位线，其中第一和第二单元串中的每一个包括地选择单元，存储单元和 第一和第二串选择单元，其顺序地形成在要连接的基板上，其中，所述接地选择单元连接到地选择线，所述存储单元连接到字线，所述第一串选择单元连接到 第一串选择线，第二串选择单元连接到第二串选择线，并且其中第一单元串的第二串选择单元具有沟道掺杂区。

公开(公告)号：US20140231899A1

公开(公告)日：2014-08-21

申请号：US14265959

申请日：2014-04-30

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jaegoo LEE ,  Byungkwan YOU ,  Youngwoo PARK ,  Kwang Soo SEOL

IPC: H01L27/115

CPC classification number: H01L21/3205 ,  H01L27/11578 ,  H01L27/11582

Abstract: Methods of manufacturing three-dimensional semiconductor devices that may include forming a first spacer on a sidewall inside a first opening formed in a first stack structure, forming a sacrificial filling pattern on the spacer to fill the first opening, forming a second stack structure including a second opening exposing the sacrificial filling pattern on the first stack structure, forming a second spacer on a sidewall inside the second opening, removing the sacrificial filling pattern and removing the first spacer and the second spacer.

Abstract translation: 制造三维半导体器件的方法，其可以包括在形成在第一堆叠结构中的第一开口内的侧壁上形成第一间隔物，在间隔物上形成牺牲填充图案以填充第一开口，形成第二堆叠结构， 在所述第一堆叠结构上暴露所述牺牲填充图案的第二开口，在所述第二开口内的侧壁上形成第二间隔件，去除所述牺牲填充图案并移除所述第一间隔件和所述第二间隔件。