公开(公告)号：US20140231899A1

公开(公告)日：2014-08-21

申请号：US14265959

申请日：2014-04-30

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jaegoo LEE ,  Byungkwan YOU ,  Youngwoo PARK ,  Kwang Soo SEOL

IPC: H01L27/115

CPC classification number: H01L21/3205 ,  H01L27/11578 ,  H01L27/11582

Abstract: Methods of manufacturing three-dimensional semiconductor devices that may include forming a first spacer on a sidewall inside a first opening formed in a first stack structure, forming a sacrificial filling pattern on the spacer to fill the first opening, forming a second stack structure including a second opening exposing the sacrificial filling pattern on the first stack structure, forming a second spacer on a sidewall inside the second opening, removing the sacrificial filling pattern and removing the first spacer and the second spacer.

Abstract translation: 制造三维半导体器件的方法，其可以包括在形成在第一堆叠结构中的第一开口内的侧壁上形成第一间隔物，在间隔物上形成牺牲填充图案以填充第一开口，形成第二堆叠结构， 在所述第一堆叠结构上暴露所述牺牲填充图案的第二开口，在所述第二开口内的侧壁上形成第二间隔件，去除所述牺牲填充图案并移除所述第一间隔件和所述第二间隔件。

公开(公告)号：US20220336489A1

公开(公告)日：2022-10-20

申请号：US17529331

申请日：2021-11-18

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Seugmin LEE ,  Kiyoon KANG ,  Kangmin KIM ,  Dongseong KIM ,  Junhyoung KIM ,  Byungkwan YOU

IPC: H01L27/11582 ,  H01L23/00

Abstract: A semiconductor device of the disclosure includes a peripheral circuit structure including a peripheral transistor, a semiconductor layer on the peripheral circuit structure, a source structure on the semiconductor layer, a gate stack structure disposed on the source structure and including insulating patterns and conductive patterns alternately stacked, a memory channel structure electrically connected to the source structure and penetrating the gate stack structure, a support structure penetrating the gate stack structure and the source structure, and an insulating layer covering the gate stack structure, the memory channel structure and the support structure. The support structure includes an outer support layer contacting side walls of the insulating patterns and side walls of the conductive patterns, and a support pattern and an inner support layer contacting an inner side wall of the outer support layer.

公开(公告)号：US20220173120A1

公开(公告)日：2022-06-02

申请号：US17465412

申请日：2021-09-02

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Seungmin LEE ,  Junhyoung KIM ,  Kangmin KIM ,  Byungkwan YOU

IPC: H01L27/11582 ,  H01L27/11519 ,  H01L27/11524 ,  H01L27/11526 ,  H01L27/11556 ,  H01L27/1157 ,  H01L27/11565 ,  H01L27/11573 ,  H01L23/522 ,  H01L23/528

Abstract: A semiconductor device includes: a substrate that includes a first region and a second region; gate electrodes stacked on the first region in a first direction, extend by different lengths in a second direction on the second region, and respectively including a pad region having an upper surface that is upwardly exposed in the second region; interlayer insulating layers alternately stacked with the gate electrodes; channel structures that extend in the first direction and penetrate through the gate electrodes; plug insulating layers alternately disposed with the interlayer insulating layers and parallel to the gate electrodes below the pad region; and contact plugs that extend in the first direction and respectively penetrate through the pad region and the plug insulating layers below the pad region. In each of the gate electrodes, the pad region has physical properties that differ from physical properties of regions other than the pad region.

公开(公告)号：US20140065810A1

公开(公告)日：2014-03-06

申请号：US14074817

申请日：2013-11-08

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Byoungkeun SON ,  Changhyun LEE ,  Jaegoo LEE ,  Kwang Soo SEOL ,  Byungkwan YOU

IPC: H01L29/66

CPC classification number: H01L29/66833 ,  H01L27/11582 ,  H01L29/7926

Abstract: A nonvolatile memory device and a method of forming the same, the device including a semiconductor substrate; a plurality of gate patterns stacked on the semiconductor substrate; inter-gate dielectric patterns between the gate patterns; active pillars sequentially penetrating the gate patterns and the inter-gate dielectric patterns to contact the semiconductor substrate; and a gate insulating layer between the active pillars and the gate patterns, wherein corners of the gate patterns adjacent to the active pillars are rounded.

Abstract translation: 非易失性存储器件及其形成方法，所述器件包括半导体衬底; 堆叠在所述半导体衬底上的多个栅极图案; 栅极图案之间的栅极间电介质图案; 依次穿过栅极图案和栅极间电介质图案以接触半导体衬底的有源支柱; 以及在活性柱和栅极图案之间的栅极绝缘层，其中与活性柱相邻的栅极图案的角部是圆形的。