公开(公告)号：US20250107178A1

公开(公告)日：2025-03-27

申请号：US18643104

申请日：2024-04-23

Applicant: Samsung Electronics Co., Ltd.

Inventor： Kyunghee Cho ,  Donghoon Hwang ,  Hyojin Kim ,  Byungho Moon ,  Doyoung Choi

IPC: H01L29/06 ,  H01L27/088 ,  H01L29/08 ,  H01L29/423 ,  H01L29/66 ,  H01L29/775 ,  H01L29/786

Abstract: An integrated circuit device includes a first fin and a second fin that extend in a first horizontal direction on a first region of a substrate, a third fin and a fourth fin that extend in the first horizontal direction on a second region of a substrate, a connected gate line at least partially surrounding a first channel region and a second channel region, and a separated gate line including a first separated portion that at least partially surrounds a third channel region and a second separated portion that at least partially surrounds a fourth channel region, where an uppermost portion of a top surface of the separated gate line is at a first vertical level, and an uppermost portion of a top surface of the connected gate line is at a second vertical level higher than the first vertical level.

公开(公告)号：US20240324164A1

公开(公告)日：2024-09-26

申请号：US18608017

申请日：2024-03-18

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Jeewoong Kim ,  Kyunghee Cho

IPC: H10B10/00 ,  H01L23/528 ,  H01L27/092 ,  H01L29/06 ,  H01L29/423 ,  H01L29/775 ,  H01L29/786

CPC classification number: H10B10/125 ,  H01L23/5283 ,  H01L27/0922 ,  H01L29/0673 ,  H01L29/42392 ,  H01L29/775 ,  H01L29/78696

Abstract: According to the inventive concept, based on the layout of a 3-dimensional stack structure enabling minimization of the planar area occupied by unit cells and simplification of the configuration of a wiring connection structure between transistors defining at least a portion of an SRAM device, an integrated circuit with a reduced size and improved reliability may be implemented.

公开(公告)号：US20240145544A1

公开(公告)日：2024-05-02

申请号：US18482154

申请日：2023-10-06

Applicant: Samsung Electronics Co., Ltd.

Inventor： Kyungho Kim ,  Myungil Kang ,  Kyunghee Cho ,  Doyoung Choi ,  Donghoon Hwang

IPC: H01L29/06 ,  H01L29/08 ,  H01L29/417 ,  H01L29/423 ,  H01L29/775 ,  H01L29/786 ,  H10B10/00

CPC classification number: H01L29/0673 ,  H01L29/0847 ,  H01L29/41733 ,  H01L29/41775 ,  H01L29/42392 ,  H01L29/775 ,  H01L29/78645 ,  H01L29/78696 ,  H10B10/125

Abstract: A semiconductor device includes an active pattern extending in a first direction; a plurality of channel layers spaced apart from each other on the active pattern in a vertical direction and including lower channel layers and upper channel layers; an intermediate insulating layer between an uppermost lower channel layer and a lowermost upper channel layer; a gate structure intersecting the active pattern and the plurality of channel layers, and extending in a second direction intersecting the first direction; a lower source/drain region on a first side of the gate structure and connected to the lower channel layers; a blocking structure on a second side of the gate structure and connected to the lower channel layers; and an upper source/drain region on at least one side of the gate structure.

公开(公告)号：US20250098278A1

公开(公告)日：2025-03-20

申请号：US18815956

申请日：2024-08-27

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Byungho Moon ,  Donghoon Hwang ,  Hyojin Kim ,  Kyunghee Cho

IPC: H01L21/8238 ,  H01L27/092 ,  H01L29/06 ,  H01L29/08 ,  H01L29/423 ,  H01L29/66 ,  H01L29/775 ,  H01L29/786

Abstract: A semiconductor device includes a substrate, lower channel layers spaced apart from each other in a vertical direction perpendicular to an upper surface of the substrate and extending in the first direction, upper channel layers on the lower channel layers, respectively, and spaced apart from each other in the vertical direction, a middle dielectric isolation structure between an uppermost lower channel layer among the lower channel layers and a lowermost upper channel layer among the upper channel layers, a lower gate structure on the lower channel layers; an upper gate structure on the upper channel layers on the lower gate structure and extending in a second direction perpendicular to the first direction. a gate isolation insulating layer between the lower gate structure and the upper gate structure, in contact with a side surface of the middle dielectric isolation structure, and extending around the lower gate structure.

公开(公告)号：US20240321886A1

公开(公告)日：2024-09-26

申请号：US18605400

申请日：2024-03-14

Applicant: Samsung Electronics Co., Ltd.

Inventor： Kyunghee Cho ,  Myungil Kang ,  Kyungho Kim ,  Kyowook Lee ,  Seunghun Lee

IPC: H01L27/092 ,  H01L29/06 ,  H01L29/417 ,  H01L29/423 ,  H01L29/775 ,  H01L29/786

CPC classification number: H01L27/092 ,  H01L29/0673 ,  H01L29/41733 ,  H01L29/42392 ,  H01L29/775 ,  H01L29/78696

Abstract: A stacked integrated circuit device includes a plurality of transistors including a pair of pull-up transistors in a first layer, a pair of pull-down transistors in a second layer that is at a different vertical level than the first layer, and a pair of pass-gate transistors in the first or second layer, a contact configured to electrically connect a source/drain region of one of the pull-up transistors, a source/drain region of one of the pull-down transistors, and a source/drain region of one of the pass-gate transistors to one another, a gate contact configured to connect a gate electrode of the other pull-up transistor to a gate electrode of the other pull-down transistor, and an upper wire on the contact and the gate contact, the upper wire extending in a first horizontal direction and being connected to the contact and the gate contact.