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    SEMICONDUCTOR DEVICE AND METHOD OF FABRICATING THE SAME
    1.
    发明申请
    SEMICONDUCTOR DEVICE AND METHOD OF FABRICATING THE SAME 有权

    公开(公告)号：US20240379409A1

    公开(公告)日：2024-11-14

    申请号：US18535089

    申请日：2023-12-11

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Jaeho Jeon ,  Wooseok Park ,  Donghoon Hwang ,  Myungil Kang ,  Kyungho Kim ,  Byungho Moon

    IPC: H01L21/762 ,  H01L23/522 ,  H01L23/528 ,  H01L29/06 ,  H01L29/66

    Abstract: A semiconductor device includes a substrate including an active pattern that is defined by a trench, a device isolation layer in the trench, a first source/drain pattern and a second source/drain pattern on the active pattern, a partition wall between the first and second source/drain patterns, a dam structure and a gate cutting pattern on the device isolation layer, and a gate spacer on a side surface of the gate cutting pattern. The first source/drain pattern is in a recess between the partition wall and the dam structure, and a lower portion of the gate spacer is interposed between the dam structure and the gate cutting pattern. A first thickness of the lower portion of the gate spacer is different from a second thickness of an upper portion of the gate spacer.

    SEMICONDUCTOR DEVICE
    3.
    发明申请
    SEMICONDUCTOR DEVICE 有权

    公开(公告)号：US20230039722A1

    公开(公告)日：2023-02-09

    申请号：US17694011

    申请日：2022-03-14

    Applicant: SAMSUNG ELECTRONICS CO., LTD.

    Inventor： Doyoung CHOI ,  Daewon Ha ,  Kyungho Kim ,  Mingyu Kim ,  Kyuman Hwang

    IPC: H01L29/423 ,  H01L29/786

    Abstract: A semiconductor device includes: a substrate including first and second regions, first and second active patterns in the first and second regions, respectively; first source/drain patterns and a first channel pattern including first semiconductor patterns; second source/drain patterns and a second channel pattern including second semiconductor patterns; first and second gate electrodes on the first and second channel patterns, respectively; and a first gate dielectric layer and a second gate dielectric layer. The first gate dielectric layer includes a first interface layer between the first channel pattern and the first gate electrode, and a first high-k dielectric layer. The second gate dielectric layer includes a second interface layer and a second high-k dielectric layer between the second channel pattern and the second gate electrode. A thickness of the first high-k dielectric layer is greater than that of the second high-k dielectric layer. A thickness of the first semiconductor pattern is less than that of the second semiconductor pattern

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