公开(公告)号：US20250098278A1

公开(公告)日：2025-03-20

申请号：US18815956

申请日：2024-08-27

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Byungho Moon ,  Donghoon Hwang ,  Hyojin Kim ,  Kyunghee Cho

IPC: H01L21/8238 ,  H01L27/092 ,  H01L29/06 ,  H01L29/08 ,  H01L29/423 ,  H01L29/66 ,  H01L29/775 ,  H01L29/786

Abstract: A semiconductor device includes a substrate, lower channel layers spaced apart from each other in a vertical direction perpendicular to an upper surface of the substrate and extending in the first direction, upper channel layers on the lower channel layers, respectively, and spaced apart from each other in the vertical direction, a middle dielectric isolation structure between an uppermost lower channel layer among the lower channel layers and a lowermost upper channel layer among the upper channel layers, a lower gate structure on the lower channel layers; an upper gate structure on the upper channel layers on the lower gate structure and extending in a second direction perpendicular to the first direction. a gate isolation insulating layer between the lower gate structure and the upper gate structure, in contact with a side surface of the middle dielectric isolation structure, and extending around the lower gate structure.

公开(公告)号：US20240379409A1

公开(公告)日：2024-11-14

申请号：US18535089

申请日：2023-12-11

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jaeho Jeon ,  Wooseok Park ,  Donghoon Hwang ,  Myungil Kang ,  Kyungho Kim ,  Byungho Moon

IPC: H01L21/762 ,  H01L23/522 ,  H01L23/528 ,  H01L29/06 ,  H01L29/66

Abstract: A semiconductor device includes a substrate including an active pattern that is defined by a trench, a device isolation layer in the trench, a first source/drain pattern and a second source/drain pattern on the active pattern, a partition wall between the first and second source/drain patterns, a dam structure and a gate cutting pattern on the device isolation layer, and a gate spacer on a side surface of the gate cutting pattern. The first source/drain pattern is in a recess between the partition wall and the dam structure, and a lower portion of the gate spacer is interposed between the dam structure and the gate cutting pattern. A first thickness of the lower portion of the gate spacer is different from a second thickness of an upper portion of the gate spacer.

公开(公告)号：US20250107178A1

公开(公告)日：2025-03-27

申请号：US18643104

申请日：2024-04-23

Applicant: Samsung Electronics Co., Ltd.

Inventor： Kyunghee Cho ,  Donghoon Hwang ,  Hyojin Kim ,  Byungho Moon ,  Doyoung Choi

IPC: H01L29/06 ,  H01L27/088 ,  H01L29/08 ,  H01L29/423 ,  H01L29/66 ,  H01L29/775 ,  H01L29/786

Abstract: An integrated circuit device includes a first fin and a second fin that extend in a first horizontal direction on a first region of a substrate, a third fin and a fourth fin that extend in the first horizontal direction on a second region of a substrate, a connected gate line at least partially surrounding a first channel region and a second channel region, and a separated gate line including a first separated portion that at least partially surrounds a third channel region and a second separated portion that at least partially surrounds a fourth channel region, where an uppermost portion of a top surface of the separated gate line is at a first vertical level, and an uppermost portion of a top surface of the connected gate line is at a second vertical level higher than the first vertical level.