公开(公告)号：US11637120B2

公开(公告)日：2023-04-25

申请号：US17708316

申请日：2022-03-30

Applicant: Samsung Electronics Co., Ltd.

Inventor： Manjoong Kim

IPC: H01L27/11575 ,  H01L23/522 ,  H01L27/115 ,  H01L27/11529 ,  H01L27/11524 ,  H01L27/1157 ,  H01L27/11582

Abstract: A vertical semiconductor device includes a substrate, a cell array region and a pad region formed on the substrate, and gate patterns and respective insulation layers. The gate patterns may be stacked in a vertical direction perpendicular to an upper surface of the substrate. Each of the gate patterns may extend in a first direction parallel to the upper surface of the substrate on the cell array region and the pad region of the substrate. The gate patterns may include pads, respectively, at edge portions thereof in the first direction. The respective insulation layers may be between adjacent gate patterns in the vertical direction. The gate patterns and the insulation layer on the pad region may serve as a pad structure, and the pad structure may include a first staircase structure having a stepped shape, a second staircase structure having a stepped shape and disposed below the first staircase structure, a flat surface portion between the first and second staircase structures, and a dummy staircase structure formed on the flat surface portion. The dummy staircase structure may be spaced apart from each of the first and second staircase structures.

公开(公告)号：US20230232632A1

公开(公告)日：2023-07-20

申请号：US18188946

申请日：2023-03-23

Applicant: Samsung Electronics Co., Ltd.

Inventor： Junhyoung KIM ,  Geunwon Lim ,  Manjoong Kim

IPC: H10B43/27 ,  H10B41/10 ,  H10B41/27 ,  H10B41/30 ,  H10B41/35 ,  H10B43/10 ,  H10B43/30 ,  H10B43/35

CPC classification number: H10B43/27 ,  H10B41/10 ,  H10B41/27 ,  H10B41/30 ,  H10B41/35 ,  H10B43/10 ,  H10B43/30 ,  H10B43/35

Abstract: A three-dimensional semiconductor memory device includes a substrate including a first connection region and a second connection region in a first direction and a cell array region between the first and second connection regions, and a first block structure on the substrate. The first block structure has a first width on the cell array region, the first block structure has a second width on the first connection region, and the first block structure has a third width on the second connection region. The first, second and third widths are parallel to a second direction intersecting the first direction, and the first width is less than the second width and is greater than the third width.

公开(公告)号：US11637121B2

公开(公告)日：2023-04-25

申请号：US16802736

申请日：2020-02-27

Applicant: Samsung Electronics Co., Ltd.

Inventor： Junhyoung Kim ,  Geunwon Lim ,  Manjoong Kim

IPC: H01L27/11519 ,  H01L27/11582 ,  H01L27/11565 ,  H01L27/11556 ,  H01L27/11524 ,  H01L27/1157

Abstract: A three-dimensional semiconductor memory device includes a substrate including a first connection region and a second connection region in a first direction and a cell array region between the first and second connection regions, and a first block structure on the substrate. The first block structure has a first width on the cell array region, the first block structure has a second width on the first connection region, and the first block structure has a third width on the second connection region. The first, second and third widths are parallel to a second direction intersecting the first direction, and the first width is less than the second width and is greater than the third width.

公开(公告)号：US20210098472A1

公开(公告)日：2021-04-01

申请号：US16892563

申请日：2020-06-04

Applicant: Samsung Electronics Co., Ltd.

Inventor： Manjoong Kim

IPC: H01L27/115 ,  H01L23/522

Abstract: A vertical semiconductor device includes a substrate, a cell array region and a pad region formed on the substrate, and gate patterns and respective insulation layers. The gate patterns may be stacked in a vertical direction perpendicular to an upper surface of the substrate. Each of the gate patterns may extend in a first direction parallel to the upper surface of the substrate on the cell array region and the pad region of the substrate. The gate patterns may include pads, respectively, at edge portions thereof in the first direction. The respective insulation layers may be between adjacent gate patterns in the vertical direction. The gate patterns and the insulation layer on the pad region may serve as a pad structure, and the pad structure may include a first staircase structure having a stepped shape, a second staircase structure having a stepped shape and disposed below the first staircase structure, a flat surface portion between the first and second staircase structures, and a dummy staircase structure formed on the flat surface portion. The dummy staircase structure may be spaced apart from each of the first and second staircase structures.

公开(公告)号：US20210020656A1

公开(公告)日：2021-01-21

申请号：US16802736

申请日：2020-02-27

Applicant: Samsung Electronics Co., Ltd.

Inventor： Junhyoung Kim ,  Geunwon Lim ,  Manjoong Kim

IPC: H01L27/11582 ,  H01L27/11565 ,  H01L27/1157 ,  H01L27/11519 ,  H01L27/11524 ,  H01L27/11556

Abstract: A three-dimensional semiconductor memory device includes a substrate including a first connection region and a second connection region in a first direction and a cell array region between the first and second connection regions, and a first block structure on the substrate. The first block structure has a first width on the cell array region, the first block structure has a second width on the first connection region, and the first block structure has a third width on the second connection region. The first, second and third widths are parallel to a second direction intersecting the first direction, and the first width is less than the second width and is greater than the third width.

公开(公告)号：US12167601B2

公开(公告)日：2024-12-10

申请号：US18188946

申请日：2023-03-23

Applicant: Samsung Electronics Co., Ltd.

Inventor： Junhyoung Kim ,  Geunwon Lim ,  Manjoong Kim

IPC: H10B41/10 ,  H10B41/27 ,  H10B41/30 ,  H10B41/35 ,  H10B43/10 ,  H10B43/27 ,  H10B43/30 ,  H10B43/35

Abstract: A three-dimensional semiconductor memory device includes a substrate including a first connection region and a second connection region in a first direction and a cell array region between the first and second connection regions, and a first block structure on the substrate. The first block structure has a first width on the cell array region, the first block structure has a second width on the first connection region, and the first block structure has a third width on the second connection region. The first, second and third widths are parallel to a second direction intersecting the first direction, and the first width is less than the second width and is greater than the third width.

公开(公告)号：US20220223615A1

公开(公告)日：2022-07-14

申请号：US17708316

申请日：2022-03-30

Applicant: Samsung Electronics Co., Ltd.

Inventor： Manjoong Kim

IPC: H01L27/11575 ,  H01L23/522 ,  H01L27/115 ,  H01L27/11529 ,  H01L27/11524 ,  H01L27/1157

Abstract: A vertical semiconductor device includes a substrate, a cell array region and a pad region formed on the substrate, and gate patterns and respective insulation layers. The gate patterns may be stacked in a vertical direction perpendicular to an upper surface of the substrate. Each of the gate patterns may extend in a first direction parallel to the upper surface of the substrate on the cell array region and the pad region of the substrate. The gate patterns may include pads, respectively, at edge portions thereof in the first direction. The respective insulation layers may be between adjacent gate patterns in the vertical direction. The gate patterns and the insulation layer on the pad region may serve as a pad structure, and the pad structure may include a first staircase structure having a stepped shape, a second staircase structure having a stepped shape and disposed below the first staircase structure, a flat surface portion between the first and second staircase structures, and a dummy staircase structure formed on the flat surface portion. The dummy staircase structure may be spaced apart from each of the first and second staircase structures.

公开(公告)号：US11296105B2

公开(公告)日：2022-04-05

申请号：US16892563

申请日：2020-06-04

Applicant: Samsung Electronics Co., Ltd.

Inventor： Manjoong Kim

IPC: H01L27/11575 ,  H01L23/522 ,  H01L27/115 ,  H01L27/11529 ,  H01L27/11524 ,  H01L27/1157

Abstract: A vertical semiconductor device includes a substrate, a cell array region and a pad region formed on the substrate, and gate patterns and respective insulation layers. The gate patterns may be stacked in a vertical direction perpendicular to an upper surface of the substrate. Each of the gate patterns may extend in a first direction parallel to the upper surface of the substrate on the cell array region and the pad region of the substrate. The gate patterns may include pads, respectively, at edge portions thereof in the first direction. The respective insulation layers may be between adjacent gate patterns in the vertical direction. The gate patterns and the insulation layer on the pad region may serve as a pad structure, and the pad structure may include a first staircase structure having a stepped shape, a second staircase structure having a stepped shape and disposed below the first staircase structure, a flat surface portion between the first and second staircase structures, and a dummy staircase structure formed on the flat surface portion. The dummy staircase structure may be spaced apart from each of the first and second staircase structures.