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    SEMICONDUCTOR DEVICE INCLUDING SUPPORT STRUCTURE, METHOD FOR MANUFACTURING THE SAME AND ELECTRONIC SYSTEM INCLUDING THE SAME
    1.
    发明申请
    SEMICONDUCTOR DEVICE INCLUDING SUPPORT STRUCTURE, METHOD FOR MANUFACTURING THE SAME AND ELECTRONIC SYSTEM INCLUDING THE SAME 有权

    公开(公告)号：US20220336489A1

    公开(公告)日：2022-10-20

    申请号：US17529331

    申请日：2021-11-18

    Applicant: SAMSUNG ELECTRONICS CO., LTD.

    Inventor： Seugmin LEE ,  Kiyoon KANG ,  Kangmin KIM ,  Dongseong KIM ,  Junhyoung KIM ,  Byungkwan YOU

    IPC: H01L27/11582 ,  H01L23/00

    Abstract: A semiconductor device of the disclosure includes a peripheral circuit structure including a peripheral transistor, a semiconductor layer on the peripheral circuit structure, a source structure on the semiconductor layer, a gate stack structure disposed on the source structure and including insulating patterns and conductive patterns alternately stacked, a memory channel structure electrically connected to the source structure and penetrating the gate stack structure, a support structure penetrating the gate stack structure and the source structure, and an insulating layer covering the gate stack structure, the memory channel structure and the support structure. The support structure includes an outer support layer contacting side walls of the insulating patterns and side walls of the conductive patterns, and a support pattern and an inner support layer contacting an inner side wall of the outer support layer.

    SEMICONDUCTOR DEVICES AND DATA STORAGE SYSTEMS INCLUDING THE SAME
    2.
    发明申请
    SEMICONDUCTOR DEVICES AND DATA STORAGE SYSTEMS INCLUDING THE SAME 有权

    公开(公告)号：US20220173120A1

    公开(公告)日：2022-06-02

    申请号：US17465412

    申请日：2021-09-02

    Applicant: SAMSUNG ELECTRONICS CO., LTD.

    Inventor： Seungmin LEE ,  Junhyoung KIM ,  Kangmin KIM ,  Byungkwan YOU

    IPC: H01L27/11582 ,  H01L27/11519 ,  H01L27/11524 ,  H01L27/11526 ,  H01L27/11556 ,  H01L27/1157 ,  H01L27/11565 ,  H01L27/11573 ,  H01L23/522 ,  H01L23/528

    Abstract: A semiconductor device includes: a substrate that includes a first region and a second region; gate electrodes stacked on the first region in a first direction, extend by different lengths in a second direction on the second region, and respectively including a pad region having an upper surface that is upwardly exposed in the second region; interlayer insulating layers alternately stacked with the gate electrodes; channel structures that extend in the first direction and penetrate through the gate electrodes; plug insulating layers alternately disposed with the interlayer insulating layers and parallel to the gate electrodes below the pad region; and contact plugs that extend in the first direction and respectively penetrate through the pad region and the plug insulating layers below the pad region. In each of the gate electrodes, the pad region has physical properties that differ from physical properties of regions other than the pad region.

    VERTICAL MEMORY DEVICES
    3.
    发明申请
    VERTICAL MEMORY DEVICES 有权

    公开(公告)号：US20220123019A1

    公开(公告)日：2022-04-21

    申请号：US17567364

    申请日：2022-01-03

    Applicant: SAMSUNG ELECTRONICS CO., LTD.

    Inventor： Junhyoung KIM ,  Seonho YOON ,  Bonghyun CHOI

    IPC: H01L27/11582 ,  H01L23/522 ,  H01L27/11556

    Abstract: A vertical memory device includes a substrate with a cell region, a through via region on opposite sides of the cell region, and a mold region surrounding the cell and through via regions, gate electrodes spaced apart from each other along a first direction vertical to an upper surface of the substrate, and extending in a second direction parallel to the upper surface of the substrate, a channel extending in the first direction on the cell region, and extending through at least a portion of the stacked gate electrodes, and a first mold including first and second layers alternately and repeatedly stacked along the first direction on the mold region, the first and second layers including different insulation materials from each other, and each of the second layers of the first mold being at the same height as and contact a corresponding one of the gate electrodes.

    THREE-DIMENSIONAL SEMICONDUCTOR MEMORY DEVICE
    7.
    发明申请
    THREE-DIMENSIONAL SEMICONDUCTOR MEMORY DEVICE 审中-公开

    公开(公告)号：US20200075605A1

    公开(公告)日：2020-03-05

    申请号：US16403795

    申请日：2019-05-06

    Applicant: SAMSUNG ELECTRONICS CO., LTD.

    Inventor： Junhyoung KIM ,  Kwang-Soo KIM ,  Bonghyun CHOI ,  Siwan KIM

    IPC: H01L27/115

    Abstract: A three-dimensional semiconductor memory device including a substrate including a cell array region and a first connection region arranged in a first direction; and a first block structure on the substrate, the first block structure including a lower stack including a plurality of lower electrodes vertically stacked on the substrate; and intermediate stacks exposing the lower stack, the intermediate stacks including a plurality of intermediate electrodes vertically stacked on the lower stack, wherein, on the cell array region, the first block structure has a first width in a second direction crossing the first direction, and wherein, on the first connection region, the first block structure has a second width, which is larger than the first width, in the second direction.

    SEMICONDUCTOR DEVICES AND DATA STORAGE SYSTEMS INCLUDING THE SAME
    9.
    发明申请
    SEMICONDUCTOR DEVICES AND DATA STORAGE SYSTEMS INCLUDING THE SAME 有权

    公开(公告)号：US20220216226A1

    公开(公告)日：2022-07-07

    申请号：US17497200

    申请日：2021-10-08

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Moorym CHOI ,  Taemok GWON ,  Junhyoung KIM ,  Hyunjae KIM ,  Youngbum WOO ,  Jongin YUN

    IPC: H01L27/11556 ,  H01L23/538 ,  H01L27/11582 ,  G11C5/06 ,  H01L29/06

    Abstract: A semiconductor device includes a first substrate including an impurity region including impurities of a first conductivity type, circuit devices on the first substrate, a lower interconnection structure electrically connected to the circuit devices, a second substrate on the lower interconnection structure and including semiconductor of the first conductivity type, gate electrodes on the second substrate and stacked and spaced apart from each other in a first direction perpendicular to an upper surface of the second substrate, channel structures penetrating the gate electrodes, and a connection structure. The channel structures may extend perpendicular to the second substrate. The channel structures may include a channel layer. The connection structure may connect the impurity region of the first substrate to the second substrate, and the connection structure may include a via including a semiconductor of a second conductivity type.

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