公开(公告)号：US12063781B2

公开(公告)日：2024-08-13

申请号：US17728759

申请日：2022-04-25

Applicant: Samsung Electronics Co., Ltd.

Inventor： Kohji Kanamori ,  Min-Yeong Song ,  Shin-Hwan Kang

IPC: H01L27/06 ,  H10B43/10 ,  H10B43/27 ,  H10B43/40 ,  H10B43/50

CPC classification number: H10B43/27 ,  H01L27/0688 ,  H10B43/10 ,  H10B43/40 ,  H10B43/50

Abstract: A vertical memory device includes a lower circuit pattern on a substrate, a plurality of gate electrodes spaced apart from another in a first direction substantially perpendicular to an upper surface of the substrate on the lower circuit pattern, a channel extending through the gate electrodes in the first direction, a memory cell block including a first common source line (CSL) extending in a second direction substantially parallel to the upper surface of the substrate, and a first contact plug connected to the lower circuit pattern and the first CSL and overlapping the first CSL in the first direction.

公开(公告)号：US11335697B2

公开(公告)日：2022-05-17

申请号：US16819907

申请日：2020-03-16

Applicant: Samsung Electronics Co., Ltd.

Inventor： Kohji Kanamori ,  Min-Yeong Song ,  Shin-Hwan Kang

IPC: H01L27/11582 ,  H01L27/11565 ,  H01L27/11573 ,  H01L27/11575 ,  H01L27/06

Abstract: A vertical memory device includes a lower circuit pattern on a substrate, a plurality of gate electrodes spaced apart from another in a first direction substantially perpendicular to an upper surface of the substrate on the lower circuit pattern, a channel extending through the gate electrodes in the first direction, a memory cell block including a first common source line (CSL) extending in a second direction substantially parallel to the upper surface of the substrate, and a first contact plug connected to the lower circuit pattern and the first CSL and overlapping the first CSL in the first direction.

公开(公告)号：US10672789B2

公开(公告)日：2020-06-02

申请号：US16120364

申请日：2018-09-03

Applicant: Samsung Electronics Co., Ltd.

Inventor： Min-Yeong Song ,  Chang-Seok Kang

IPC: H01L27/11565 ,  H01L27/11582 ,  H01L29/10 ,  H01L29/423 ,  H01L27/1157 ,  H01L21/311 ,  H01L21/02 ,  H01L21/3065 ,  H01L21/768 ,  H01L27/11575

Abstract: A vertical semiconductor device may include a first gate pattern, second gate patterns, a first channel hole, a first semiconductor pattern, a second channel hole, and a second semiconductor pattern. The first gate pattern may extend in a first direction on a substrate including first and second regions. The first direction may be parallel to an upper surface of the substrate, and a portion of the first gate pattern on the second region may include a first opening. The second gate patterns may be vertically stacked and spaced apart from each other on the first gate pattern, and each of the second gate patterns may extend in the first direction. The first channel hole may extend through the second gate patterns and the first gate pattern and expose a first portion of the substrate on the first region of the substrate. The first semiconductor pattern may be at a lower portion of the first channel hole. The second channel hole may extend through the second gate patterns and expose a second portion of the substrate on the second region of the substrate, and the second channel hole may be disposed within an area of the first opening in a plan view, wherein the first opening has a larger area than the second channel hole in a plan view. The second semiconductor pattern may be at a lower portion of the second channel hole.