公开(公告)号：US10672789B2

公开(公告)日：2020-06-02

申请号：US16120364

申请日：2018-09-03

Applicant: Samsung Electronics Co., Ltd.

Inventor： Min-Yeong Song ,  Chang-Seok Kang

IPC: H01L27/11565 ,  H01L27/11582 ,  H01L29/10 ,  H01L29/423 ,  H01L27/1157 ,  H01L21/311 ,  H01L21/02 ,  H01L21/3065 ,  H01L21/768 ,  H01L27/11575

Abstract: A vertical semiconductor device may include a first gate pattern, second gate patterns, a first channel hole, a first semiconductor pattern, a second channel hole, and a second semiconductor pattern. The first gate pattern may extend in a first direction on a substrate including first and second regions. The first direction may be parallel to an upper surface of the substrate, and a portion of the first gate pattern on the second region may include a first opening. The second gate patterns may be vertically stacked and spaced apart from each other on the first gate pattern, and each of the second gate patterns may extend in the first direction. The first channel hole may extend through the second gate patterns and the first gate pattern and expose a first portion of the substrate on the first region of the substrate. The first semiconductor pattern may be at a lower portion of the first channel hole. The second channel hole may extend through the second gate patterns and expose a second portion of the substrate on the second region of the substrate, and the second channel hole may be disposed within an area of the first opening in a plan view, wherein the first opening has a larger area than the second channel hole in a plan view. The second semiconductor pattern may be at a lower portion of the second channel hole.

公开(公告)号：US10763167B2

公开(公告)日：2020-09-01

申请号：US16243338

申请日：2019-01-09

Applicant: Samsung Electronics Co., Ltd.

Inventor： Kyung-Hwan Lee ,  Chang-Seok Kang ,  Yong-Seok Kim ,  Jun-Hee Lim ,  Kohji Kanamori

IPC: H01L21/768 ,  H01L23/522 ,  H01L27/115 ,  H01L21/3213 ,  H01L21/311

Abstract: A vertical semiconductor device includes a conductive pattern structure in which insulation patterns and conductive patterns alternately and repeatedly stacked on the substrate. The conductive pattern structure includes an edge portion having a stair-stepped shape. Each of the conductive patterns includes a pad region corresponding to an upper surface of a stair in the edge portion. A pad conductive pattern is disposed to contact a portion of an upper surface of the pad region. A mask pattern is disposed on an upper surface of the pad conductive pattern. A contact plug penetrates the mask pattern to contact the pad conductive pattern.

公开(公告)号：US09349879B2

公开(公告)日：2016-05-24

申请号：US14554859

申请日：2014-11-26

Applicant: Samsung Electronics Co., Ltd.

Inventor： Ju-Hyung Kim ,  Chang-Seok Kang ,  Sung-Il Chang ,  Jung-Dal Choi

IPC: H01L29/788 ,  H01L29/792 ,  H01L27/115 ,  H01L29/66 ,  H01L29/423 ,  H01L21/28 ,  H01L29/51

CPC classification number: H01L29/792 ,  H01L21/28273 ,  H01L21/28282 ,  H01L27/115 ,  H01L27/11517 ,  H01L27/11529 ,  H01L27/11563 ,  H01L27/11568 ,  H01L29/42324 ,  H01L29/4234 ,  H01L29/42348 ,  H01L29/51 ,  H01L29/513 ,  H01L29/517 ,  H01L29/518 ,  H01L29/66825 ,  H01L29/66833 ,  H01L29/788 ,  H01L29/7883

Abstract: A non-volatile memory device may include a semiconductor substrate and an isolation layer on the semiconductor substrate wherein the isolation layer defines an active region of the semiconductor substrate. A tunnel insulation layer may be provided on the active region of the semiconductor substrate, and a charge storage pattern may be provided on the tunnel insulation layer. An interface layer pattern may be provided on the charge storage pattern, and a blocking insulation pattern may be provided on the interface layer pattern. Moreover, the block insulation pattern may include a high-k dielectric material, and the interface layer pattern and the blocking insulation pattern may include different materials. A control gate electrode may be provided on the blocking insulating layer so that the blocking insulation pattern is between the interface layer pattern and the control gate electrode. Related methods are also discussed.

Abstract translation: 非易失性存储器件可以包括半导体衬底和半导体衬底上的隔离层，其中隔离层限定半导体衬底的有源区。 可以在半导体衬底的有源区上设置隧道绝缘层，并且可以在隧道绝缘层上设置电荷存储图案。 可以在电荷存储图案上提供界面层图案，并且可以在界面层图案上提供阻挡绝缘图案。 此外，块绝缘图案可以包括高k介电材料，并且界面层图案和阻挡绝缘图案可以包括不同的材料。 可以在阻挡绝缘层上设置控制栅电极，使得阻挡绝缘图案位于界面层图案和控制栅电极之间。 还讨论了相关方法。

公开(公告)号：US20190393239A1

公开(公告)日：2019-12-26

申请号：US16263417

申请日：2019-01-31

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： KYUNG-HWAN LEE ,  Chang-Seok Kang ,  Yong-Seok Kim ,  Jun-Hee Lim ,  Kohji Kanamori

IPC: H01L27/11582 ,  H01L27/11565

Abstract: A vertical semiconductor device includes a conductive pattern structure, a memory layer, a pillar structure, and second and third insulation patterns. The conductive pattern structure includes conductive patterns and insulation layers, and may include a first portion extending in a first direction and a second portion protruding from a sidewall of the first portion. The conductive pattern structures are arranged in a second direction perpendicular to the first direction to form a trench therebetween. The memory layer is formed on sidewalls of the conductive pattern structures. The pillar structures in the trench, each including a channel pattern and a first insulation pattern formed on the memory layer, are spaced apart from each other in the first direction. The second insulation pattern is formed between the pillar structures. The third insulation pattern is formed between some pillar structures, and has a shape different from a shape of the second insulation pattern.

公开(公告)号：US10199389B2

公开(公告)日：2019-02-05

申请号：US15485334

申请日：2017-04-12

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jong-Won Kim ,  Chang-Seok Kang ,  Young-Woo Park ,  Jae-Goo Lee ,  Jae-Duk Lee

IPC: H01L27/1157 ,  H01L27/11582 ,  H01L27/11565 ,  H01L23/528

Abstract: A non-volatile memory device is provided. The non-volatile memory device includes a channel structure that is located on a substrate and extends perpendicularly to the substrate, a conductive pattern that extends perpendicularly to the substrate and is spaced apart from the channel structure, an electrode structure that is located between the channel structure and the conductive pattern, and comprises a plurality of gate patterns and a plurality of insulation patterns that are alternately laminated. An insulating layer that contacts with a top surface of the conductive pattern is formed along side surfaces of the electrode structure. The top surface of the conductive pattern is formed to be lower than the top surface of the channel structure.

公开(公告)号：US09646984B2

公开(公告)日：2017-05-09

申请号：US15264902

申请日：2016-09-14

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jong-Won Kim ,  Chang-Seok Kang ,  Young-Woo Park ,  Jae-Goo Lee ,  Jae-Duk Lee

IPC: H01L27/115 ,  H01L27/1157 ,  H01L27/11582

CPC classification number: H01L27/1157 ,  H01L27/11582

Abstract: A non-volatile memory device is provided. The non-volatile memory device includes a channel structure that is located on a substrate and extends perpendicularly to the substrate, a conductive pattern that extends perpendicularly to the substrate and is spaced apart from the channel structure, an electrode structure that is located between the channel structure and the conductive pattern, and comprises a plurality of gate patterns and a plurality of insulation patterns that are alternately laminated. An insulating layer that contacts with a top surface of the conductive pattern is formed along side surfaces of the electrode structure. The top surface of the conductive pattern is formed to be lower than the top surface of the channel structure.

公开(公告)号：US10896728B2

公开(公告)日：2021-01-19

申请号：US16243281

申请日：2019-01-09

Applicant: Samsung Electronics Co., Ltd.

Inventor： Kohji Kanamori ,  Chang-Seok Kang ,  Yong-Seok Kim ,  Kyung-Hwan Lee

IPC: G11C13/00 ,  G11C7/12 ,  G11C16/34 ,  G11C16/10 ,  G11C16/14 ,  G11C11/56

Abstract: In a method of writing data in a nonvolatile memory device including a plurality of cell strings, each of the plurality of cell strings includes a plurality of memory cells disposed in a vertical direction. A program target page is divided into a plurality of subpages. The program target page is connected to one of a plurality of wordlines. Each of the plurality of subpages includes memory cells that are physically spaced apart from one another. A program operation is sequentially performed on the plurality of subpages. A program verification operation is performed on the program target page including the plurality of subpages at a time.

公开(公告)号：US10680011B2

公开(公告)日：2020-06-09

申请号：US16263417

申请日：2019-01-31

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Kyung-Hwan Lee ,  Chang-Seok Kang ,  Yong-Seok Kim ,  Jun-Hee Lim ,  Kohji Kanamori

IPC: H01L29/792 ,  H01L27/11582 ,  H01L27/11565

Abstract: A vertical semiconductor device includes a conductive pattern structure, a memory layer, a pillar structure, and second and third insulation patterns. The conductive pattern structure includes conductive patterns and insulation layers, and may include a first portion extending in a first direction and a second portion protruding from a sidewall of the first portion. The conductive pattern structures are arranged in a second direction perpendicular to the first direction to form a trench therebetween. The memory layer is formed on sidewalls of the conductive pattern structures. The pillar structures in the trench, each including a channel pattern and a first insulation pattern formed on the memory layer, are spaced apart from each other in the first direction. The second insulation pattern is formed between the pillar structures. The third insulation pattern is formed between some pillar structures, and has a shape different from a shape of the second insulation pattern.

公开(公告)号：US09905568B2

公开(公告)日：2018-02-27

申请号：US15251580

申请日：2016-08-30

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Yong-Hoon Son ,  Jong-Won Kim ,  Chang-Seok Kang ,  Young-Woo Park ,  Jae-Duk Lee ,  Kyung-Hyun Kim ,  Byeong-Ju Kim ,  Phil-Ouk Nam ,  Kwang-Chul Park ,  Yeon-Sil Sohn ,  Jin-I Lee ,  Won-Bong Jung

IPC: H01L27/115 ,  H01L29/66 ,  H01L27/1157 ,  H01L27/11565 ,  H01L27/11582

CPC classification number: H01L27/1157 ,  H01L27/11565 ,  H01L27/11582 ,  H01L29/66833

Abstract: A nonvolatile memory device includes a conductive line disposed on a substrate and vertically extended from the substrate, a first channel layer disposed on the substrate and vertically extended from the substrate, wherein the first channel layer is spaced apart from the conductive line, a second channel layer vertically extended from the substrate, wherein the second channel layer is disposed between the first channel layer and the conductive line, a first gate electrode disposed between the conductive line and the second channel layer, wherein the first gate electrode includes a first portion having a first thickness and a second portion having a second thickness that is different from the first thickness, and a second gate electrode disposed between the first channel layer and the second channel layer, wherein the second gate electrode has the second thickness.