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1.发明授权公开(公告)号：US12235757B2
公开(公告)日：2025-02-25
申请号：US18318906
申请日：2023-05-17
Applicant: Samsung Electronics Co., Ltd.
Inventor： Sungrae Kim , Sungyong Cho , Minho Maeing , Gilyoung Kang , Hyeran Kim , Chisung Oh
Abstract: A memory system includes a host system having a memory controller therein, which is configured to generate a command address signal. The memory controller includes a first bit signal generator configured to generate a data signal as a plurality of data bits, a second bit signal generator configured to generate a command address bus inversion bit (CABIB) having a high or low logic level that is a function of a number of data bits within the data signal having a predetermined logic level, and a parity bit generator configured to set a parity signal to a first logic level when a total number of data bits within the data signal and the CABIB having a high logic level is an even number. A storage system is also provided, which is configured to write or read data in response to the command address signal received from the host system. The memory controller is configured to set the CABIB to a high logic level when: (i) “n”, which is a number of bits included in the command address signal, is a positive integer greater than one, and (ii) a number of data bits within the data signal having a low logic level is greater than or equal to (n/2)−1.
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2.发明公开公开(公告)号：US20230376414A1
公开(公告)日：2023-11-23
申请号：US18318906
申请日：2023-05-17
Applicant: Samsung Electronics Co., Ltd.
Inventor： Sungrae Kim , Sungyong Cho , Minho Maeing , Gilyoung Kang , Hyeran Kim , Chisung Oh
IPC: G06F12/06
CPC classification number: G06F12/06
Abstract: A memory system includes a host system having a memory controller therein, which is configured to generate a command address signal. The memory controller includes a first bit signal generator configured to generate a data signal as a plurality of data bits, a second bit signal generator configured to generate a command address bus inversion bit (CABIB) having a high or low logic level that is a function of a number of data bits within the data signal having a predetermined logic level, and a parity bit generator configured to set a parity signal to a first logic level when a total number of data bits within the data signal and the CABIB having a high logic level is an even number. A storage system is also provided, which is configured to write or read data in response to the command address signal received from the host system. The memory controller is configured to set the CABIB to a high logic level when: (i) “n”, which is a number of bits included in the command address signal, is a positive integer greater than one, and (ii) a number of data bits within the data signal having a low logic level is greater than or equal to (n/2)−1.
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