公开(公告)号：US12235757B2

公开(公告)日：2025-02-25

申请号：US18318906

申请日：2023-05-17

Applicant: Samsung Electronics Co., Ltd.

Inventor： Sungrae Kim ,  Sungyong Cho ,  Minho Maeing ,  Gilyoung Kang ,  Hyeran Kim ,  Chisung Oh

IPC: G06F11/10 ,  G06F12/06

Abstract: A memory system includes a host system having a memory controller therein, which is configured to generate a command address signal. The memory controller includes a first bit signal generator configured to generate a data signal as a plurality of data bits, a second bit signal generator configured to generate a command address bus inversion bit (CABIB) having a high or low logic level that is a function of a number of data bits within the data signal having a predetermined logic level, and a parity bit generator configured to set a parity signal to a first logic level when a total number of data bits within the data signal and the CABIB having a high logic level is an even number. A storage system is also provided, which is configured to write or read data in response to the command address signal received from the host system. The memory controller is configured to set the CABIB to a high logic level when: (i) “n”, which is a number of bits included in the command address signal, is a positive integer greater than one, and (ii) a number of data bits within the data signal having a low logic level is greater than or equal to (n/2)−1.

公开(公告)号：US10784184B2

公开(公告)日：2020-09-22

申请号：US16263408

申请日：2019-01-31

Applicant: Samsung Electronics Co., Ltd.

Inventor： Soojung Rho ,  Chisung Oh ,  Kyomin Sohn ,  Yong-Ki Kim ,  Jong-Ho Moon ,  SeungHan Woo ,  Jaeyoun Youn

IPC: H01L23/48 ,  H01L23/538 ,  H01L23/528 ,  H01L23/522 ,  H01L25/065

Abstract: A semiconductor device includes first to M-th semiconductor dies stacked in a first direction. Each of the first to M-th semiconductor dies includes a substrate, first to K-th through silicon vias passing through the substrate in the first direction, and a first circuit to receive power through a power supply line electrically connected to the first through silicon via. Each of first to K-th through silicon vias of the N-th semiconductor die is electrically connected to a through silicon via of first to K-th through silicon vias of the (N+1)-th semiconductor die that is spaced apart therefrom in a plan view.

公开(公告)号：US20240146335A1

公开(公告)日：2024-05-02

申请号：US18336285

申请日：2023-06-16

Applicant: Samsung Electronics Co., Ltd.

Inventor： Sungrae Kim ,  Gilyoung Kang ,  Yujung Song ,  Hyeran Kim ,  Chisung Oh

IPC: H03M13/29 ,  G06F3/06 ,  G06F11/10

CPC classification number: H03M13/2909 ,  G06F3/0611 ,  G06F3/0659 ,  G06F3/0673 ,  G06F11/10

Abstract: A semiconductor memory device includes a memory cell array and an on-die error correction code (ECC) engine. The on-die ECC engine, during a write operation, generates a second main data by encoding a first main data with a random binary code, performs an ECC encoding on the second main data to generate a parity data and stores the second main data and the parity data in a target page in the memory cell array. The on-die ECC engine, during a read operation, reads the second main data and the parity data from the target page, performs an ECC decoding on the second main data based on the parity data to generate a syndrome in parallel with generating the first main data by encoding the second main data with the random binary code and corrects at least one error bit in the first main data based on the syndrome.

公开(公告)号：US11947810B2

公开(公告)日：2024-04-02

申请号：US17743137

申请日：2022-05-12

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Sungrae Kim ,  Hyeran Kim ,  Myungkyu Lee ,  Chisung Oh ,  Kijun Lee ,  Sunghye Cho ,  Sanguhn Cha

IPC: G06F3/06

CPC classification number: G06F3/0619 ,  G06F3/0655 ,  G06F3/0656 ,  G06F3/0679

Abstract: A semiconductor memory device includes a memory cell array and a cyclic redundancy check (CRC) engine. The memory cell array includes a plurality of volatile memory cells coupled to respective ones of a plurality of word-lines and respective ones of a plurality of bit-lines. The CRC engine, during a memory operation on the memory cell array, detects an error in a main data and a system parity data provided from a memory controller external to the semiconductor memory device through a link, generates an error flag indicating whether the detected error corresponds to either a first type of error associated with the link or a second type of error associated with the volatile memory cells based on the system parity data and transmit the error flag to the memory controller.

公开(公告)号：US20240005204A1

公开(公告)日：2024-01-04

申请号：US18054176

申请日：2022-11-10

Applicant: Samsung Electronics Co., Ltd.

Inventor： Kiwon Lee ,  Sung-Rae Kim ,  Gilyoung Kang ,  Hye-Ran Kim ,  Chisung Oh

IPC: G06N20/00

CPC classification number: G06N20/00

Abstract: A semiconductor device includes a sequence data generator, which is configured to generate sequence data on a plurality of data lines, and a symbol changer. The symbol changer is configured to generate a training pattern from the sequence data by replacing, for each of the plurality of data lines, each occurrence of a bitstream within the sequence data that has a predetermined symbol with an alternative symbol. The sequence data generator may include a sequence generator, which is configured to generate a pseudo random binary sequence (PRBS), based on a seed value for each clock cycle.

公开(公告)号：US20230376414A1

公开(公告)日：2023-11-23

申请号：US18318906

申请日：2023-05-17

Applicant: Samsung Electronics Co., Ltd.

Inventor： Sungrae Kim ,  Sungyong Cho ,  Minho Maeing ,  Gilyoung Kang ,  Hyeran Kim ,  Chisung Oh

IPC: G06F12/06

CPC classification number: G06F12/06

Abstract: A memory system includes a host system having a memory controller therein, which is configured to generate a command address signal. The memory controller includes a first bit signal generator configured to generate a data signal as a plurality of data bits, a second bit signal generator configured to generate a command address bus inversion bit (CABIB) having a high or low logic level that is a function of a number of data bits within the data signal having a predetermined logic level, and a parity bit generator configured to set a parity signal to a first logic level when a total number of data bits within the data signal and the CABIB having a high logic level is an even number. A storage system is also provided, which is configured to write or read data in response to the command address signal received from the host system. The memory controller is configured to set the CABIB to a high logic level when: (i) “n”, which is a number of bits included in the command address signal, is a positive integer greater than one, and (ii) a number of data bits within the data signal having a low logic level is greater than or equal to (n/2)−1.

公开(公告)号：US20250038151A1

公开(公告)日：2025-01-30

申请号：US18591889

申请日：2024-02-29

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Kyuha Shim ,  Chisung Oh ,  Useung Shin

IPC: H01L25/065

Abstract: According to some implementations, provided is a semiconductor device including: a first semiconductor chip including first through-vias, and first front pads electrically connected to the first through-vias; and a second semiconductor chip disposed below the first semiconductor chip, and including a substrate, a circuit layer disposed below the substrate, second front pads below the circuit layer, rear pads disposed on the substrate and electrically connected to the corresponding first front pads, second through-vias penetrating through the substrate and electrically connected to the second front pads, and a rear redistribution layer electrically connecting the second through-vias and the rear pads, wherein at least one of the rear pads is spaced apart from a corresponding one of the second through-vias in a horizontal direction, and overlaps a corresponding one of the first through-vias in a vertical direction.

公开(公告)号：US12170533B2

公开(公告)日：2024-12-17

申请号：US18336285

申请日：2023-06-16

Applicant: Samsung Electronics Co., Ltd.

Inventor： Sungrae Kim ,  Gilyoung Kang ,  Yujung Song ,  Hyeran Kim ,  Chisung Oh

IPC: H03M13/29 ,  G06F3/06 ,  G06F11/10 ,  G11C11/4096 ,  G11C29/42 ,  G11C29/52 ,  H03M13/15

Abstract: A semiconductor memory device includes a memory cell array and an on-die error correction code (ECC) engine. The on-die ECC engine, during a write operation, generates a second main data by encoding a first main data with a random binary code, performs an ECC encoding on the second main data to generate a parity data and stores the second main data and the parity data in a target page in the memory cell array. The on-die ECC engine, during a read operation, reads the second main data and the parity data from the target page, performs an ECC decoding on the second main data based on the parity data to generate a syndrome in parallel with generating the first main data by encoding the second main data with the random binary code and corrects at least one error bit in the first main data based on the syndrome.

公开(公告)号：US11942968B2

公开(公告)日：2024-03-26

申请号：US17975034

申请日：2022-10-27

Applicant: Samsung Electronics Co., Ltd.

Inventor： Changkyu Seol ,  Sungrae Kim ,  Chisung Oh ,  Junghwan Choi

IPC: H03M13/00 ,  H03M5/14 ,  H04L1/00

CPC classification number: H03M5/145 ,  H04L1/0009 ,  H04L1/0014

Abstract: A transmitter includes an encoder configured to divide a first number of binary input bits of an input data signal into a first bit group and a second bit group, generate a first intermediate bit group and a second intermediate bit group by manipulating the first bit group and the second bit group differently based on a value of the first bit group, and generate a first symbol group and a second symbol group by encoding the first intermediate bit group and the second intermediate bit group, each of the first symbol group and the second symbol group including a plurality of symbols, and each of the plurality of symbols having three different voltage levels. The transmitter includes a driver configured to generate an output data signal by concatenating the first symbol group and the second symbol group.

公开(公告)号：US11888476B2

公开(公告)日：2024-01-30

申请号：US17591093

申请日：2022-02-02

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Daehyun Kwon ,  Hyejung Kwon ,  Hyeran Kim ,  Chisung Oh

IPC: H03K19/017 ,  H03K19/00 ,  H03K19/17736 ,  H03K19/17772

CPC classification number: H03K19/01742 ,  H03K19/0005 ,  H03K19/1774 ,  H03K19/17772

Abstract: An apparatus, a memory device, and a method for storing parameter codes with respect to asymmetric on-die-termination (ODT) are provided. The apparatus is connected to an external device via a signal line, and includes: an on-die termination (ODT) circuit set in a first ODT state; a plurality of signal pins, each of which is connected to the signal line; and an ODT control circuit configured to: identify whether a second ODT state of the external device corresponds to the first ODT state, and based on the apparatus being an asymmetric ODT in which the first ODT state and the second ODT state are different, provide an asymmetric ODT parameter code to the external device, and disable the ODT circuit when a signal is not transmitted through the signal line.