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    TRANSMITTING DEVICES THAT PROVIDE TRANMISSION SIGNALS HAVING ENLARGED DATA EYES
    1.
    发明公开
    TRANSMITTING DEVICES THAT PROVIDE TRANMISSION SIGNALS HAVING ENLARGED DATA EYES 审中-公开

    公开(公告)号：US20240073081A1

    公开(公告)日：2024-02-29

    申请号：US18327306

    申请日：2023-06-01

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Seongyeal Yang ,  Moonchul Choi ,  Sungyong Cho ,  Jaehyeok Baek

    IPC: H04L27/36

    CPC classification number: H04L27/36

    Abstract: Provided is a transmitting device for enlarging the size of a data eye of a transmission signal. The transmitting device includes an output driver including a plurality of driver circuits that drive a plurality of multi-level signals onto an output node, and a logic circuit configured to detect a direction of a pull-up or pull-down operation of each of the plurality of driver circuits by transitions of the plurality of driver control signals and generate pulse signals. The plurality of multi-level signals are driven based on a plurality of driver control signals and pulse signals, respectively, and the logic circuit provides a pulse signal to at least one static driver circuit connected to a driver control signal that does not transition, from among the plurality of driver circuits.

    MEMORY DEVICE PERFORMING TIMING SKEW AND OFFSET CALIBRATION
    3.
    发明申请
    MEMORY DEVICE PERFORMING TIMING SKEW AND OFFSET CALIBRATION 有权

    公开(公告)号：US20250014632A1

    公开(公告)日：2025-01-09

    申请号：US18600736

    申请日：2024-03-10

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Jaehyeok Baek ,  Sungyong Cho ,  Hyeran Kim

    IPC: G11C11/4076 ,  G11C11/4093 ,  G11C11/4099

    Abstract: A memory device includes a data input/output (I/O) pin, an output driver, a multi-level receiver and a calibrator. The output driver is connected to the data I/O pin, and generates an internal input signal based on a first clock signal. The multi-level receiver is connected to the data I/O pin, and includes a plurality of samplers. The plurality of samplers generate a plurality of decision signals by sampling the internal input signal based on a reference voltage and a second clock signal. The calibrator detects and compensates at least one of timing skew and offset associated with the plurality of samplers based on the plurality of decision signals. The internal input signal is a multi-level signal having three or more voltage levels that are different from each other.

    MEMORY SYSTEMS AND CONTROLLERS FOR GENERATING A COMMAND ADDRESS AND METHODS OF OPERATING SAME
    4.
    发明公开
    MEMORY SYSTEMS AND CONTROLLERS FOR GENERATING A COMMAND ADDRESS AND METHODS OF OPERATING SAME 审中-公开

    公开(公告)号：US20230376414A1

    公开(公告)日：2023-11-23

    申请号：US18318906

    申请日：2023-05-17

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Sungrae Kim ,  Sungyong Cho ,  Minho Maeing ,  Gilyoung Kang ,  Hyeran Kim ,  Chisung Oh

    IPC: G06F12/06

    CPC classification number: G06F12/06

    Abstract: A memory system includes a host system having a memory controller therein, which is configured to generate a command address signal. The memory controller includes a first bit signal generator configured to generate a data signal as a plurality of data bits, a second bit signal generator configured to generate a command address bus inversion bit (CABIB) having a high or low logic level that is a function of a number of data bits within the data signal having a predetermined logic level, and a parity bit generator configured to set a parity signal to a first logic level when a total number of data bits within the data signal and the CABIB having a high logic level is an even number. A storage system is also provided, which is configured to write or read data in response to the command address signal received from the host system. The memory controller is configured to set the CABIB to a high logic level when: (i) “n”, which is a number of bits included in the command address signal, is a positive integer greater than one, and (ii) a number of data bits within the data signal having a low logic level is greater than or equal to (n/2)−1.

    Device of generating reference voltages for multi-level signaling and memory system including the same
    5.
    发明授权
    Device of generating reference voltages for multi-level signaling and memory system including the same 有权

    公开(公告)号：US12237037B2

    公开(公告)日：2025-02-25

    申请号：US18151784

    申请日：2023-01-09

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Sang-Hoon Kim ,  Sungyong Cho

    IPC: G11C7/00 ,  G11C5/14 ,  H04L25/49

    Abstract: A reference voltage generation device includes a noise information generation circuit configured to generate power noise information based on a first power noise and a second power noise, the first power noise and the second power noise generated based on a first power and a second power supplied to a first electronic device and propagated from the first electronic device to a second electronic device through a communication line, and the first electronic device and the second electronic device configured to perform data communication using a multi-level signaling scheme. The device includes a reference voltage generation circuit configured to generate three or more reference voltages for the multi-level signaling scheme based on the power noise information, and the second electronic device is configured to use the three or more reference voltages.

    Transmitting devices that provide transmission signals having enlarged data eyes
    6.
    发明授权
    Transmitting devices that provide transmission signals having enlarged data eyes 有权

    公开(公告)号：US12170589B2

    公开(公告)日：2024-12-17

    申请号：US18327306

    申请日：2023-06-01

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Seongyeal Yang ,  Moonchul Choi ,  Sungyong Cho ,  Jaehyeok Baek

    IPC: H04L27/36

    Abstract: Provided is a transmitting device for enlarging the size of a data eye of a transmission signal. The transmitting device includes an output driver including a plurality of driver circuits that drive a plurality of multi-level signals onto an output node, and a logic circuit configured to detect a direction of a pull-up or pull-down operation of each of the plurality of driver circuits by transitions of the plurality of driver control signals and generate pulse signals. The plurality of multi-level signals are driven based on a plurality of driver control signals and pulse signals, respectively, and the logic circuit provides a pulse signal to at least one static driver circuit connected to a driver control signal that does not transition, from among the plurality of driver circuits.

    Semiconductor memory device and memory system including the same
    7.
    发明授权
    Semiconductor memory device and memory system including the same 有权

    公开(公告)号：US11955159B2

    公开(公告)日：2024-04-09

    申请号：US17703049

    申请日：2022-03-24

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Sungyong Cho ,  Kiheung Kim ,  Hyeran Kim

    IPC: G11C11/406 ,  G11C11/408 ,  H01L25/065 ,  H03M13/00 ,  H03M13/11

    CPC classification number: G11C11/40615 ,  G11C11/4085 ,  H03M13/1105 ,  H03M13/611 ,  H01L25/0657 ,  H01L2225/06541

    Abstract: A semiconductor memory device includes a memory cell array including a plurality of memory cell rows, a row hammer management circuit and a refresh control circuit. The row hammer management circuit counts the number of times of access associated with each of the plurality of memory cell rows in response to an active command from an external memory controller to store the counted values in each of the plurality of memory cell rows as count data, determines a hammer address associated with at least one of the plurality of memory cell rows, which is intensively accessed more than a predetermined reference number of times, based on the counted values, and performs an internal read-update-write operation. The refresh control circuit receives the hammer address and to perform a hammer refresh operation on victim memory cell rows which are physically adjacent to a memory cell row corresponding to the hammer address.

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