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1.发明授权公开(公告)号：US12235757B2
公开(公告)日：2025-02-25
申请号：US18318906
申请日：2023-05-17
Applicant: Samsung Electronics Co., Ltd.
Inventor： Sungrae Kim , Sungyong Cho , Minho Maeing , Gilyoung Kang , Hyeran Kim , Chisung Oh
Abstract: A memory system includes a host system having a memory controller therein, which is configured to generate a command address signal. The memory controller includes a first bit signal generator configured to generate a data signal as a plurality of data bits, a second bit signal generator configured to generate a command address bus inversion bit (CABIB) having a high or low logic level that is a function of a number of data bits within the data signal having a predetermined logic level, and a parity bit generator configured to set a parity signal to a first logic level when a total number of data bits within the data signal and the CABIB having a high logic level is an even number. A storage system is also provided, which is configured to write or read data in response to the command address signal received from the host system. The memory controller is configured to set the CABIB to a high logic level when: (i) “n”, which is a number of bits included in the command address signal, is a positive integer greater than one, and (ii) a number of data bits within the data signal having a low logic level is greater than or equal to (n/2)−1.
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公开(公告)号：US20240146335A1
公开(公告)日：2024-05-02
申请号：US18336285
申请日：2023-06-16
Applicant: Samsung Electronics Co., Ltd.
Inventor： Sungrae Kim , Gilyoung Kang , Yujung Song , Hyeran Kim , Chisung Oh
CPC classification number: H03M13/2909 , G06F3/0611 , G06F3/0659 , G06F3/0673 , G06F11/10
Abstract: A semiconductor memory device includes a memory cell array and an on-die error correction code (ECC) engine. The on-die ECC engine, during a write operation, generates a second main data by encoding a first main data with a random binary code, performs an ECC encoding on the second main data to generate a parity data and stores the second main data and the parity data in a target page in the memory cell array. The on-die ECC engine, during a read operation, reads the second main data and the parity data from the target page, performs an ECC decoding on the second main data based on the parity data to generate a syndrome in parallel with generating the first main data by encoding the second main data with the random binary code and corrects at least one error bit in the first main data based on the syndrome.
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Patent Agency Ranking
公开(公告)号：US20240005204A1
公开(公告)日：2024-01-04
申请号：US18054176
申请日：2022-11-10
Applicant: Samsung Electronics Co., Ltd.
Inventor： Kiwon Lee , Sung-Rae Kim , Gilyoung Kang , Hye-Ran Kim , Chisung Oh
IPC: G06N20/00
CPC classification number: G06N20/00
Abstract: A semiconductor device includes a sequence data generator, which is configured to generate sequence data on a plurality of data lines, and a symbol changer. The symbol changer is configured to generate a training pattern from the sequence data by replacing, for each of the plurality of data lines, each occurrence of a bitstream within the sequence data that has a predetermined symbol with an alternative symbol. The sequence data generator may include a sequence generator, which is configured to generate a pseudo random binary sequence (PRBS), based on a seed value for each clock cycle.
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4.发明公开公开(公告)号：US20230376414A1
公开(公告)日：2023-11-23
申请号：US18318906
申请日：2023-05-17
Applicant: Samsung Electronics Co., Ltd.
Inventor： Sungrae Kim , Sungyong Cho , Minho Maeing , Gilyoung Kang , Hyeran Kim , Chisung Oh
IPC: G06F12/06
CPC classification number: G06F12/06
Abstract: A memory system includes a host system having a memory controller therein, which is configured to generate a command address signal. The memory controller includes a first bit signal generator configured to generate a data signal as a plurality of data bits, a second bit signal generator configured to generate a command address bus inversion bit (CABIB) having a high or low logic level that is a function of a number of data bits within the data signal having a predetermined logic level, and a parity bit generator configured to set a parity signal to a first logic level when a total number of data bits within the data signal and the CABIB having a high logic level is an even number. A storage system is also provided, which is configured to write or read data in response to the command address signal received from the host system. The memory controller is configured to set the CABIB to a high logic level when: (i) “n”, which is a number of bits included in the command address signal, is a positive integer greater than one, and (ii) a number of data bits within the data signal having a low logic level is greater than or equal to (n/2)−1.
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公开(公告)号：US12170533B2
公开(公告)日：2024-12-17
申请号：US18336285
申请日：2023-06-16
Applicant: Samsung Electronics Co., Ltd.
Inventor： Sungrae Kim , Gilyoung Kang , Yujung Song , Hyeran Kim , Chisung Oh
Abstract: A semiconductor memory device includes a memory cell array and an on-die error correction code (ECC) engine. The on-die ECC engine, during a write operation, generates a second main data by encoding a first main data with a random binary code, performs an ECC encoding on the second main data to generate a parity data and stores the second main data and the parity data in a target page in the memory cell array. The on-die ECC engine, during a read operation, reads the second main data and the parity data from the target page, performs an ECC decoding on the second main data based on the parity data to generate a syndrome in parallel with generating the first main data by encoding the second main data with the random binary code and corrects at least one error bit in the first main data based on the syndrome.
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公开(公告)号：US20240029808A1
公开(公告)日：2024-01-25
申请号：US18174186
申请日：2023-02-24
Applicant: Samsung Electronics Co., Ltd.
Inventor： Yujung Song , Sungrae Kim , Gilyoung Kang , Hyeran Kim , Chisung Oh
CPC classification number: G11C29/42 , G11C29/46 , G11C29/1201
Abstract: A semiconductor memory device includes a memory cell array, an on-die error correction code (ECC) engine and a control logic circuit. The on-die ECC engine includes a first latch and a second latch. The control logic circuit sets the semiconductor memory device to a test mode in response to a first mode register set command. The on-die ECC engine, in the test mode, cuts off a connection with the memory cell array, receives a test data, stores the test data in the first latch, performs an ECC decoding on the test data stored in the first latch and a test parity data, stored in the second latch in response to a read command and provides an external device with a severity signal indicating whether the test data and the test parity data includes at least one error bit and the at least one error bit is correctable.
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7.发明公开公开(公告)号：US20230377669A1
公开(公告)日：2023-11-23
申请号：US18134776
申请日：2023-04-14
Applicant: Samsung Electronics Co., Ltd.
Inventor： Wonyoung Choi , Gilyoung Kang , Sungrae Kim , Hyeran Kim , Jeongseok Park , Changkyu Seol
Abstract: A memory device, an operating method of the memory device, and a test system including the memory device. The memory device may include a decoder group configured to receive a plurality of codewords including a plurality of symbols from outside of the memory device and to decode the plurality of codewords into data patterns, a memory cell array configured to store the data patterns received from the decoder group and including a plurality of memory cells, and an encoder configured to encode the data patterns into the plurality of codewords including the plurality of symbols. The plurality of codewords may include illegal codewords and normal codewords, and the decoder group may be further configured to convert the illegal codewords among the plurality of codewords into fixed patterns, and the encoder may be configured to output the plurality of codewords to the outside of the memory device.
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