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    Semiconductor memory device and memory system including the same
    1.
    发明授权
    Semiconductor memory device and memory system including the same 有权

    公开(公告)号：US11955159B2

    公开(公告)日：2024-04-09

    申请号：US17703049

    申请日：2022-03-24

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Sungyong Cho ,  Kiheung Kim ,  Hyeran Kim

    IPC: G11C11/406 ,  G11C11/408 ,  H01L25/065 ,  H03M13/00 ,  H03M13/11

    CPC classification number: G11C11/40615 ,  G11C11/4085 ,  H03M13/1105 ,  H03M13/611 ,  H01L25/0657 ,  H01L2225/06541

    Abstract: A semiconductor memory device includes a memory cell array including a plurality of memory cell rows, a row hammer management circuit and a refresh control circuit. The row hammer management circuit counts the number of times of access associated with each of the plurality of memory cell rows in response to an active command from an external memory controller to store the counted values in each of the plurality of memory cell rows as count data, determines a hammer address associated with at least one of the plurality of memory cell rows, which is intensively accessed more than a predetermined reference number of times, based on the counted values, and performs an internal read-update-write operation. The refresh control circuit receives the hammer address and to perform a hammer refresh operation on victim memory cell rows which are physically adjacent to a memory cell row corresponding to the hammer address.

    Output driver and semiconductor memory device having the same
    2.
    发明授权
    Output driver and semiconductor memory device having the same 有权

    公开(公告)号：US11626143B2

    公开(公告)日：2023-04-11

    申请号：US17481995

    申请日：2021-09-22

    Applicant: SAMSUNG ELECTRONICS CO., LTD. ,  RESEARCH & BUSINESS FOUNDATION SUNGKYUNKWAN UNIVERSITY

    Inventor： Hyeran Kim ,  Junyeol Lee ,  Jung-Hoon Chun

    IPC: G11C5/14 ,  G11C8/10

    Abstract: An output driver includes a pre driver including pre driving circuits, each including first and second pre pumps, and a main driver including main driving circuits, each including first and second main pumps. Each of the first and second pre pumps includes a first driving capacitor, and each of the first and second main pumps includes a second driving capacitor. During a first half cycle of a clock signal, the first pre pump and the first main pump perform a precharge operation, and the second pre pump and the second main pump perform a first driving operation, and during a second half cycle of the clock signal, the first pre pump and the first main pump perform the first driving operation, and the second pre pump and the second main pump perform the precharge operation. Capacitances of the first and second driving capacitors are different.

    Memory systems and controllers for generating a command address and methods of operating same
    3.
    发明授权
    Memory systems and controllers for generating a command address and methods of operating same 有权

    公开(公告)号：US12235757B2

    公开(公告)日：2025-02-25

    申请号：US18318906

    申请日：2023-05-17

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Sungrae Kim ,  Sungyong Cho ,  Minho Maeing ,  Gilyoung Kang ,  Hyeran Kim ,  Chisung Oh

    IPC: G06F11/10 ,  G06F12/06

    Abstract: A memory system includes a host system having a memory controller therein, which is configured to generate a command address signal. The memory controller includes a first bit signal generator configured to generate a data signal as a plurality of data bits, a second bit signal generator configured to generate a command address bus inversion bit (CABIB) having a high or low logic level that is a function of a number of data bits within the data signal having a predetermined logic level, and a parity bit generator configured to set a parity signal to a first logic level when a total number of data bits within the data signal and the CABIB having a high logic level is an even number. A storage system is also provided, which is configured to write or read data in response to the command address signal received from the host system. The memory controller is configured to set the CABIB to a high logic level when: (i) “n”, which is a number of bits included in the command address signal, is a positive integer greater than one, and (ii) a number of data bits within the data signal having a low logic level is greater than or equal to (n/2)−1.

    SEMICONDUCTOR MEMORY DEVICE AND METHODS OF OPERATION
    4.
    发明公开
    SEMICONDUCTOR MEMORY DEVICE AND METHODS OF OPERATION 审中-公开

    公开(公告)号：US20230185460A1

    公开(公告)日：2023-06-15

    申请号：US18076628

    申请日：2022-12-07

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Kiheung Kim ,  Taeyoung Oh ,  Hyeran Kim ,  Sungyong Cho ,  Kyungsoo Ha

    IPC: G06F3/06

    CPC classification number: G06F3/0619 ,  G06F3/0653 ,  G06F3/0659 ,  G06F3/0673

    Abstract: A semiconductor memory device includes a memory cell array, a row hammer management circuit and a control logic circuit. The memory cell array includes a plurality of memory cell rows. The row hammer management circuit counts the number of instances of access of each of the memory cell rows, such as in response to the receipt of an active command, to store the counted values in count cells of each of the memory cell rows as count data and, in response to a first command, initiates an internal read-update-write operation to read the count data, to update the read count data, and to write the updated count data in the count cells. The control logic circuit may performs an internal write operation to write the updated count data in the count cells during a second write time interval that is smaller than a first write time interval associated with a normal write operation.

    MEMORY DEVICE PERFORMING TIMING SKEW AND OFFSET CALIBRATION
    5.
    发明申请
    MEMORY DEVICE PERFORMING TIMING SKEW AND OFFSET CALIBRATION 有权

    公开(公告)号：US20250014632A1

    公开(公告)日：2025-01-09

    申请号：US18600736

    申请日：2024-03-10

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Jaehyeok Baek ,  Sungyong Cho ,  Hyeran Kim

    IPC: G11C11/4076 ,  G11C11/4093 ,  G11C11/4099

    Abstract: A memory device includes a data input/output (I/O) pin, an output driver, a multi-level receiver and a calibrator. The output driver is connected to the data I/O pin, and generates an internal input signal based on a first clock signal. The multi-level receiver is connected to the data I/O pin, and includes a plurality of samplers. The plurality of samplers generate a plurality of decision signals by sampling the internal input signal based on a reference voltage and a second clock signal. The calibrator detects and compensates at least one of timing skew and offset associated with the plurality of samplers based on the plurality of decision signals. The internal input signal is a multi-level signal having three or more voltage levels that are different from each other.

    Semiconductor memory device and memory system including the same
    7.
    发明授权
    Semiconductor memory device and memory system including the same 有权

    公开(公告)号：US11947810B2

    公开(公告)日：2024-04-02

    申请号：US17743137

    申请日：2022-05-12

    Applicant: SAMSUNG ELECTRONICS CO., LTD.

    Inventor： Sungrae Kim ,  Hyeran Kim ,  Myungkyu Lee ,  Chisung Oh ,  Kijun Lee ,  Sunghye Cho ,  Sanguhn Cha

    IPC: G06F3/06

    CPC classification number: G06F3/0619 ,  G06F3/0655 ,  G06F3/0656 ,  G06F3/0679

    Abstract: A semiconductor memory device includes a memory cell array and a cyclic redundancy check (CRC) engine. The memory cell array includes a plurality of volatile memory cells coupled to respective ones of a plurality of word-lines and respective ones of a plurality of bit-lines. The CRC engine, during a memory operation on the memory cell array, detects an error in a main data and a system parity data provided from a memory controller external to the semiconductor memory device through a link, generates an error flag indicating whether the detected error corresponds to either a first type of error associated with the link or a second type of error associated with the volatile memory cells based on the system parity data and transmit the error flag to the memory controller.

    MEMORY SYSTEMS AND CONTROLLERS FOR GENERATING A COMMAND ADDRESS AND METHODS OF OPERATING SAME
    8.
    发明公开
    MEMORY SYSTEMS AND CONTROLLERS FOR GENERATING A COMMAND ADDRESS AND METHODS OF OPERATING SAME 审中-公开

    公开(公告)号：US20230376414A1

    公开(公告)日：2023-11-23

    申请号：US18318906

    申请日：2023-05-17

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Sungrae Kim ,  Sungyong Cho ,  Minho Maeing ,  Gilyoung Kang ,  Hyeran Kim ,  Chisung Oh

    IPC: G06F12/06

    CPC classification number: G06F12/06

    Abstract: A memory system includes a host system having a memory controller therein, which is configured to generate a command address signal. The memory controller includes a first bit signal generator configured to generate a data signal as a plurality of data bits, a second bit signal generator configured to generate a command address bus inversion bit (CABIB) having a high or low logic level that is a function of a number of data bits within the data signal having a predetermined logic level, and a parity bit generator configured to set a parity signal to a first logic level when a total number of data bits within the data signal and the CABIB having a high logic level is an even number. A storage system is also provided, which is configured to write or read data in response to the command address signal received from the host system. The memory controller is configured to set the CABIB to a high logic level when: (i) “n”, which is a number of bits included in the command address signal, is a positive integer greater than one, and (ii) a number of data bits within the data signal having a low logic level is greater than or equal to (n/2)−1.

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